Several rk3588 board DTS files override pinctrl-0 for i2c, i2s, pcie,
pwm, sdmmc, spdif, spi and uart nodes without re-specifying
pinctrl-names. While the property is inherited from the base SoC DTSI,
add it explicitly to the board-level overrides for consistency with
other nodes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-12-924df9db884a@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&pwm6 {
pinctrl-0 = <&pwm6m1_pins>;
+ pinctrl-names = "default";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
+ pinctrl-names = "default";
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
&i2c7 {
pinctrl-0 = <&i2c7m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
es8316: audio-codec@10 {
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
+ pinctrl-names = "default";
status = "okay";
i2s0_8ch_p0: port {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
/* rk3588 preferred debug out */
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
/* uart/232/485 */
&uart0 {
pinctrl-0 = <&uart0m2_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
+ pinctrl-names = "default";
status = "okay";
fan@18 {
&i2c1 {
pinctrl-0 = <&i2c1m4_xfer>;
+ pinctrl-names = "default";
};
&i2c6 {
pinctrl-0 = <&i2c6m4_xfer>;
+ pinctrl-names = "default";
};
&i2c7 {
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
+ pinctrl-names = "default";
status = "okay";
typec-portc@22 {
/* Mule-ATtiny debug UART; typically baudrate 9600 */
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
/* Main debug interface on P20 micro-USB B port and P21 header */
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
/* RS485 on P19 */
&uart3 {
pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
+ pinctrl-names = "default";
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* Mule-ATtiny UPDI flashing UART */
&uart7 {
pinctrl-0 = <&uart7m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&pcie2x1l2 {
pinctrl-0 = <&pcie2_0_rst>;
+ pinctrl-names = "default";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pwm8 {
pinctrl-0 = <&pwm8m2_pins>;
+ pinctrl-names = "default";
status = "okay";
};
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
+ pinctrl-names = "default";
};
&i2s0_8ch {
&pwm1 {
pinctrl-0 = <&pwm1m1_pins>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&pwm3 {
pinctrl-0 = <&pwm3m1_pins>;
+ pinctrl-names = "default";
status = "okay";
};
&uart9 {
pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&spdif_tx1 {
pinctrl-0 = <&spdif1m2_tx>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
+ pinctrl-names = "default";
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
&i2c1 {
pinctrl-0 = <&i2c1m0_xfer>;
+ pinctrl-names = "default";
};
&i2c1m0_xfer {
&i2c2 {
pinctrl-0 = <&i2c2m3_xfer>;
+ pinctrl-names = "default";
};
&i2c2m3_xfer {
&i2c3 {
pinctrl-0 = <&i2c3m0_xfer>;
+ pinctrl-names = "default";
};
&i2c4 {
pinctrl-0 = <&i2c4m4_xfer>;
+ pinctrl-names = "default";
status = "okay";
vdd_npu_s0: regulator@42 {
&i2c5 {
pinctrl-0 = <&i2c5m1_xfer>;
+ pinctrl-names = "default";
};
&i2c5m1_xfer {
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
+ pinctrl-names = "default";
};
&mdio0 {
&spi0 {
pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>;
+ pinctrl-names = "default";
};
&spi2 {
/* Routed to UART0 on the Q7 connector */
&uart2 {
pinctrl-0 = <&uart2m2_xfer>;
+ pinctrl-names = "default";
};
/* Mule-ATtiny UPDI */
&uart4 {
pinctrl-0 = <&uart4m2_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};
&uart9 {
pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
status = "okay";
};