--- /dev/null
+From 2800aadc18a64c96b051bcb7da8a7df7d505db3f Mon Sep 17 00:00:00 2001
+From: Jiri Kosina <jkosina@suse.cz>
+Date: Tue, 2 Mar 2021 11:26:55 +0100
+Subject: iwlwifi: Fix softirq/hardirq disabling in iwl_pcie_enqueue_hcmd()
+
+From: Jiri Kosina <jkosina@suse.cz>
+
+commit 2800aadc18a64c96b051bcb7da8a7df7d505db3f upstream.
+
+It's possible for iwl_pcie_enqueue_hcmd() to be called with hard IRQs
+disabled (e.g. from LED core). We can't enable BHs in such a situation.
+
+Turn the unconditional BH-enable/BH-disable code into
+hardirq-disable/conditional-enable.
+
+This fixes the warning below.
+
+ WARNING: CPU: 1 PID: 1139 at kernel/softirq.c:178 __local_bh_enable_ip+0xa5/0xf0
+ CPU: 1 PID: 1139 Comm: NetworkManager Not tainted 5.12.0-rc1-00004-gb4ded168af79 #7
+ Hardware name: LENOVO 20K5S22R00/20K5S22R00, BIOS R0IET38W (1.16 ) 05/31/2017
+ RIP: 0010:__local_bh_enable_ip+0xa5/0xf0
+ Code: f7 69 e8 ee 23 14 00 fb 66 0f 1f 44 00 00 65 8b 05 f0 f4 f7 69 85 c0 74 3f 48 83 c4 08 5b c3 65 8b 05 9b fe f7 69 85 c0 75 8e <0f> 0b eb 8a 48 89 3c 24 e8 4e 20 14 00 48 8b 3c 24 eb 91 e8 13 4e
+ RSP: 0018:ffffafd580b13298 EFLAGS: 00010046
+ RAX: 0000000000000000 RBX: 0000000000000201 RCX: 0000000000000000
+ RDX: 0000000000000003 RSI: 0000000000000201 RDI: ffffffffc1272389
+ RBP: ffff96517ae4c018 R08: 0000000000000001 R09: 0000000000000000
+ R10: ffffafd580b13178 R11: 0000000000000001 R12: ffff96517b060000
+ R13: 0000000000000000 R14: ffffffff80000000 R15: 0000000000000001
+ FS: 00007fc604ebefc0(0000) GS:ffff965267480000(0000) knlGS:0000000000000000
+ CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+ CR2: 000055fb3fef13b2 CR3: 0000000109112004 CR4: 00000000003706e0
+ Call Trace:
+ ? _raw_spin_unlock_bh+0x1f/0x30
+ iwl_pcie_enqueue_hcmd+0x5d9/0xa00 [iwlwifi]
+ iwl_trans_txq_send_hcmd+0x6c/0x430 [iwlwifi]
+ iwl_trans_send_cmd+0x88/0x170 [iwlwifi]
+ ? lock_acquire+0x277/0x3d0
+ iwl_mvm_send_cmd+0x32/0x80 [iwlmvm]
+ iwl_mvm_led_set+0xc2/0xe0 [iwlmvm]
+ ? led_trigger_event+0x46/0x70
+ led_trigger_event+0x46/0x70
+ ieee80211_do_open+0x5c5/0xa20 [mac80211]
+ ieee80211_open+0x67/0x90 [mac80211]
+ __dev_open+0xd4/0x150
+ __dev_change_flags+0x19e/0x1f0
+ dev_change_flags+0x23/0x60
+ do_setlink+0x30d/0x1230
+ ? lock_is_held_type+0xb4/0x120
+ ? __nla_validate_parse.part.7+0x57/0xcb0
+ ? __lock_acquire+0x2e1/0x1a50
+ __rtnl_newlink+0x560/0x910
+ ? __lock_acquire+0x2e1/0x1a50
+ ? __lock_acquire+0x2e1/0x1a50
+ ? lock_acquire+0x277/0x3d0
+ ? sock_def_readable+0x5/0x290
+ ? lock_is_held_type+0xb4/0x120
+ ? find_held_lock+0x2d/0x90
+ ? sock_def_readable+0xb3/0x290
+ ? lock_release+0x166/0x2a0
+ ? lock_is_held_type+0x90/0x120
+ rtnl_newlink+0x47/0x70
+ rtnetlink_rcv_msg+0x25c/0x470
+ ? netlink_deliver_tap+0x97/0x3e0
+ ? validate_linkmsg+0x350/0x350
+ netlink_rcv_skb+0x50/0x100
+ netlink_unicast+0x1b2/0x280
+ netlink_sendmsg+0x336/0x450
+ sock_sendmsg+0x5b/0x60
+ ____sys_sendmsg+0x1ed/0x250
+ ? copy_msghdr_from_user+0x5c/0x90
+ ___sys_sendmsg+0x88/0xd0
+ ? lock_is_held_type+0xb4/0x120
+ ? find_held_lock+0x2d/0x90
+ ? lock_release+0x166/0x2a0
+ ? __fget_files+0xfe/0x1d0
+ ? __sys_sendmsg+0x5e/0xa0
+ __sys_sendmsg+0x5e/0xa0
+ ? lockdep_hardirqs_on_prepare+0xd9/0x170
+ do_syscall_64+0x33/0x80
+ entry_SYSCALL_64_after_hwframe+0x44/0xae
+ RIP: 0033:0x7fc605c9572d
+ Code: 28 89 54 24 1c 48 89 74 24 10 89 7c 24 08 e8 da ee ff ff 8b 54 24 1c 48 8b 74 24 10 41 89 c0 8b 7c 24 08 b8 2e 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 33 44 89 c7 48 89 44 24 08 e8 2e ef ff ff 48
+ RSP: 002b:00007fffc83789f0 EFLAGS: 00000293 ORIG_RAX: 000000000000002e
+ RAX: ffffffffffffffda RBX: 000055ef468570c0 RCX: 00007fc605c9572d
+ RDX: 0000000000000000 RSI: 00007fffc8378a30 RDI: 000000000000000c
+ RBP: 0000000000000010 R08: 0000000000000000 R09: 0000000000000000
+ R10: 0000000000000000 R11: 0000000000000293 R12: 0000000000000000
+ R13: 00007fffc8378b80 R14: 00007fffc8378b7c R15: 0000000000000000
+ irq event stamp: 170785
+ hardirqs last enabled at (170783): [<ffffffff9609a8c2>] __local_bh_enable_ip+0x82/0xf0
+ hardirqs last disabled at (170784): [<ffffffff96a8613d>] _raw_read_lock_irqsave+0x8d/0x90
+ softirqs last enabled at (170782): [<ffffffffc1272389>] iwl_pcie_enqueue_hcmd+0x5d9/0xa00 [iwlwifi]
+ softirqs last disabled at (170785): [<ffffffffc1271ec6>] iwl_pcie_enqueue_hcmd+0x116/0xa00 [iwlwifi]
+
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+Tested-by: Sedat Dilek <sedat.dilek@gmail.com> # LLVM/Clang v12.0.0-rc3
+Acked-by: Luca Coelho <luciano.coelho@intel.com>
+Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
+Link: https://lore.kernel.org/r/nycvar.YFH.7.76.2103021125430.12405@cbobk.fhfr.pm
+Signed-off-by: Jari Ruusu <jariruusu@protonmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wireless/intel/iwlwifi/pcie/tx.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
++++ b/drivers/net/wireless/intel/iwlwifi/pcie/tx.c
+@@ -1473,6 +1473,7 @@ static int iwl_pcie_enqueue_hcmd(struct
+ u32 cmd_pos;
+ const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
+ u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
++ unsigned long flags2;
+
+ if (WARN(!trans->wide_cmd_header &&
+ group_id > IWL_ALWAYS_LONG_GROUP,
+@@ -1556,10 +1557,10 @@ static int iwl_pcie_enqueue_hcmd(struct
+ goto free_dup_buf;
+ }
+
+- spin_lock_bh(&txq->lock);
++ spin_lock_irqsave(&txq->lock, flags2);
+
+ if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
+- spin_unlock_bh(&txq->lock);
++ spin_unlock_irqrestore(&txq->lock, flags2);
+
+ IWL_ERR(trans, "No space in command queue\n");
+ iwl_op_mode_cmd_queue_full(trans->op_mode);
+@@ -1720,7 +1721,7 @@ static int iwl_pcie_enqueue_hcmd(struct
+ spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
+
+ out:
+- spin_unlock_bh(&txq->lock);
++ spin_unlock_irqrestore(&txq->lock, flags2);
+ free_dup_buf:
+ if (idx < 0)
+ kfree(dup_buf);
--- /dev/null
+From foo@baz Tue May 4 09:25:24 AM CEST 2021
+From: Matt Redfearn <matt.redfearn@mips.com>
+Date: Mon, 26 Feb 2018 17:02:43 +0000
+Subject: MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV
+
+From: Matt Redfearn <matt.redfearn@mips.com>
+
+commit 18ba210a29d08ea96025cb9d19c2eebf65846330 upstream
+
+Remove the need to check that __mips_isa_rev is defined by using the
+newly added MIPS_ISA_REV.
+
+Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: Paul Burton <paul.burton@mips.com>
+Cc: "Maciej W. Rozycki" <macro@mips.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/18675/
+Signed-off-by: James Hogan <jhogan@kernel.org>
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/mips/include/asm/cpu-features.h | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -11,6 +11,7 @@
+
+ #include <asm/cpu.h>
+ #include <asm/cpu-info.h>
++#include <asm/isa-rev.h>
+ #include <cpu-feature-overrides.h>
+
+ /*
+@@ -493,7 +494,7 @@
+ # define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
+ #endif
+
+-#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
++#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)
+ /*
+ * Some systems share FTLB RAMs between threads within a core (siblings in
+ * kernel parlance). This means that FTLB entries may become invalid at almost
+@@ -525,7 +526,7 @@
+ # define cpu_has_shared_ftlb_entries \
+ (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
+ # endif
+-#endif /* SMP && __mips_isa_rev >= 6 */
++#endif /* SMP && MIPS_ISA_REV >= 6 */
+
+ #ifndef cpu_has_shared_ftlb_ram
+ # define cpu_has_shared_ftlb_ram 0
--- /dev/null
+From foo@baz Tue May 4 09:25:24 AM CEST 2021
+From: Romain Naour <romain.naour@gmail.com>
+Date: Tue, 20 Apr 2021 22:12:10 +0100
+Subject: mips: Do not include hi and lo in clobber list for R6
+
+From: Romain Naour <romain.naour@gmail.com>
+
+commit 1d7ba0165d8206ac073f7ac3b14fc0836b66eae7 upstream
+
+>From [1]
+"GCC 10 (PR 91233) won't silently allow registers that are not
+architecturally available to be present in the clobber list anymore,
+resulting in build failure for mips*r6 targets in form of:
+...
+.../sysdep.h:146:2: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the current target
+ 146 | __asm__ volatile ( \
+ | ^~~~~~~
+
+This is because base R6 ISA doesn't define hi and lo registers w/o DSP
+extension. This patch provides the alternative clobber list for r6 targets
+that won't include those registers."
+
+Since kernel 5.4 and mips support for generic vDSO [2], the kernel fail to
+build for mips r6 cpus with gcc 10 for the same reason as glibc.
+
+[1] https://sourceware.org/git/?p=glibc.git;a=commit;h=020b2a97bb15f807c0482f0faee2184ed05bcad8
+[2] '24640f233b46 ("mips: Add support for generic vDSO")'
+
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/mips/vdso/gettimeofday.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/vdso/gettimeofday.c
++++ b/arch/mips/vdso/gettimeofday.c
+@@ -18,6 +18,12 @@
+ #include <asm/unistd.h>
+ #include <asm/vdso.h>
+
++#if MIPS_ISA_REV < 6
++#define VDSO_SYSCALL_CLOBBERS "hi", "lo",
++#else
++#define VDSO_SYSCALL_CLOBBERS
++#endif
++
+ #ifdef CONFIG_MIPS_CLOCK_VSYSCALL
+
+ static __always_inline long gettimeofday_fallback(struct timeval *_tv,
+@@ -34,7 +40,9 @@ static __always_inline long gettimeofday
+ : "=r" (ret), "=r" (error)
+ : "r" (tv), "r" (tz), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+- "$14", "$15", "$24", "$25", "hi", "lo", "memory");
++ "$14", "$15", "$24", "$25",
++ VDSO_SYSCALL_CLOBBERS
++ "memory");
+
+ return error ? -ret : ret;
+ }
+@@ -55,7 +63,9 @@ static __always_inline long clock_gettim
+ : "=r" (ret), "=r" (error)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+- "$14", "$15", "$24", "$25", "hi", "lo", "memory");
++ "$14", "$15", "$24", "$25",
++ VDSO_SYSCALL_CLOBBERS
++ "memory");
+
+ return error ? -ret : ret;
+ }
--- /dev/null
+From foo@baz Tue May 4 09:25:24 AM CEST 2021
+From: Matt Redfearn <matt.redfearn@mips.com>
+Date: Mon, 26 Feb 2018 17:02:42 +0000
+Subject: MIPS: Introduce isa-rev.h to define MIPS_ISA_REV
+
+From: Matt Redfearn <matt.redfearn@mips.com>
+
+commit 1690905240fd45cc04e873312df8574631c9f595 upstream
+
+There are multiple instances in the kernel where we need to include or
+exclude particular instructions based on the ISA revision of the target
+processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev
+define. However, when targeting MIPS I - V, this define is absent. This
+leads to each use of __mips_isa_rev having to check that it is defined
+first. To simplify this, introduce the isa-rev.h header which always
+exports MIPS_ISA_REV. The name is changed so as to avoid confusion with
+the compiler builtin and to avoid accidentally using the builtin.
+MIPS_ISA_REV is defined to the compilers builtin if provided, or 0,
+which satisfies all current usages.
+
+Suggested-by: Paul Burton <paul.burton@mips.com>
+Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
+Reviewed-by: Maciej W. Rozycki <macro@mips.com>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/18676/
+Signed-off-by: James Hogan <jhogan@kernel.org>
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/mips/include/asm/isa-rev.h | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 arch/mips/include/asm/isa-rev.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/isa-rev.h
+@@ -0,0 +1,24 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2018 MIPS Tech, LLC
++ * Author: Matt Redfearn <matt.redfearn@mips.com>
++ */
++
++#ifndef __MIPS_ASM_ISA_REV_H__
++#define __MIPS_ASM_ISA_REV_H__
++
++/*
++ * The ISA revision level. This is 0 for MIPS I to V and N for
++ * MIPS{32,64}rN.
++ */
++
++/* If the compiler has defined __mips_isa_rev, believe it. */
++#ifdef __mips_isa_rev
++#define MIPS_ISA_REV __mips_isa_rev
++#else
++/* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */
++#define MIPS_ISA_REV 0
++#endif
++
++
++#endif /* __MIPS_ASM_ISA_REV_H__ */
bpf-fix-backport-of-bpf-restrict-unknown-scalars-of-mixed-signed-bounds-for-unprivileged.patch
bpf-fix-up-selftests-after-backports-were-fixed.patch
net-usb-ax88179_178a-initialize-local-variables-before-use.patch
+iwlwifi-fix-softirq-hardirq-disabling-in-iwl_pcie_enqueue_hcmd.patch
+mips-introduce-isa-rev.h-to-define-mips_isa_rev.patch
+mips-cpu-features.h-replace-__mips_isa_rev-with-mips_isa_rev.patch
+mips-do-not-include-hi-and-lo-in-clobber-list-for-r6.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
