clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets

Add LCDC{0,1} clocks and resets entries to the r9a09g047 CPG driver.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/c1b5afcef8068d4d074aff97e30b4d64b7c38eaf.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 9e7bb65acea6b924eecb6f45f4b5b65dd0a1bd17..94158b6834e6e0ef6ea0ec7fa7b3adf980ad7c23 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -518,6 +518,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(15) | BIT(14))),
        DEF_MOD("dsi_0_pllref_clk",             CLK_QEXTAL, 14, 12, 7, 12,
                                                BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("lcdc_0_clk_a",                 CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
+                                               BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
+       DEF_MOD("lcdc_0_clk_p",                 CLK_PLLDTY_DIV16, 14, 14, 7, 14,
+                                               BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
+       DEF_MOD("lcdc_0_clk_d",                 CLK_SMUX2_DSI0_CLK, 14, 15, 7, 15,
+                                               BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
        DEF_MOD("ge3d_clk",                     CLK_PLLVDO_GPU, 15, 0, 7, 16,
                                                BUS_MSTOP(3, BIT(4))),
        DEF_MOD("ge3d_axi_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -528,6 +534,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(2, BIT(15))),
        DEF_MOD("dsi_0_vclk2",                  CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
                                                BUS_MSTOP(9, BIT(15) | BIT(14))),
+       DEF_MOD("lcdc_1_clk_a",                 CLK_PLLDTY_ACPU_DIV2, 26, 8, 10, 30,
+                                               BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
+       DEF_MOD("lcdc_1_clk_p",                 CLK_PLLDTY_DIV16, 26, 9, 10, 31,
+                                               BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
+       DEF_MOD("lcdc_1_clk_d",                 CLK_SMUX2_DSI1_CLK, 26, 10, 11, 0,
+                                               BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -605,10 +617,12 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
        DEF_RST(13, 7, 6, 8),           /* DSI_0_PRESETN */
        DEF_RST(13, 8, 6, 9),           /* DSI_0_ARESETN */
+       DEF_RST(13, 12, 6, 13),         /* LCDC_0_RESET_N */
        DEF_RST(13, 13, 6, 14),         /* GE3D_RESETN */
        DEF_RST(13, 14, 6, 15),         /* GE3D_AXI_RESETN */
        DEF_RST(13, 15, 6, 16),         /* GE3D_ACE_RESETN */
        DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
+       DEF_RST(17, 14, 8, 15),         /* LCDC_1_RESET_N */
 };
 
 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {