/* Configure DSI_Control register */
val = (dsi_dev->lanes - 1) << 1;
- val |= TC358768_DSI_CONTROL_TXMD;
+ if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
+ val |= TC358768_DSI_CONTROL_TXMD;
if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
val |= TC358768_DSI_CONTROL_HSCKMD;
return;
}
+ /* Enable HS mode for video TX */
+ tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL,
+ TC358768_DSI_CONTROL_TXMD,
+ TC358768_DSI_CONTROL_TXMD);
+
/* clear FrmStop and RstPtr */
tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);