drm/amd/display: Enable HUBP/OPTC/DPP power gating

[Why & How]
Enable driver power gating on DCN42 for HUBP OPTC
and DPP HW blocks.

Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index c2f8554cdcd3526da8ae39809cdca199e5d73a0b..227eb13176636ad35d01c32da889316d94cab04a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -694,9 +694,12 @@ static const struct dc_debug_options debug_defaults_drv = {
        .force_abm_enable = false,
        .clock_trace = true,
        .disable_pplib_clock_request = false,
-       .disable_dpp_power_gate = true,
-       .disable_hubp_power_gate = true,
-       .disable_optc_power_gate = true,
+       .ignore_pg = false,
+       .disable_dpp_power_gate = false,
+       .disable_hubp_power_gate = false,
+       .disable_optc_power_gate = false,
+       .disable_dsc_power_gate = false,
+       .disable_dio_power_gate = true,
        .pipe_split_policy = MPC_SPLIT_AVOID,
        .force_single_disp_pipe_split = false,
        .disable_dcc = DCC_ENABLE,
@@ -758,12 +761,10 @@ static const struct dc_debug_options debug_defaults_drv = {
        .min_disp_clk_khz = 50000,
        .static_screen_wait_frames = 2,
        .disable_z10 = false,
-       .ignore_pg = false,
        .disable_stutter_for_wm_program = true,
        .min_deep_sleep_dcfclk_khz = 8000,
        .replay_skip_crtc_disabled = true,
        .psr_skip_crtc_disable = true,
-       .disable_dio_power_gate = true,
 };
 
 static const struct dc_check_config config_defaults = {