]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: usb: Enable RX aggregation for RTL8922AU
authorBitterblue Smith <rtl8821cerfe2@gmail.com>
Sun, 19 Apr 2026 13:43:53 +0000 (16:43 +0300)
committerPing-Ke Shih <pkshih@realtek.com>
Wed, 29 Apr 2026 03:18:50 +0000 (11:18 +0800)
It uses the same settings as RTL8852CU, but the register and bit names
have "BE" instead of "AX".

Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/bd9e444f-257c-48c8-8adb-f58432b2c5c2@gmail.com
drivers/net/wireless/realtek/rtw89/usb.c
drivers/net/wireless/realtek/rtw89/usb.h

index a08e43c8275e4f373864c449a761fab7f8e6f070..c6d55e669776cca2dabc0ff1a47183b2ebd773a9 100644 (file)
@@ -803,6 +803,17 @@ static void rtw89_usb_rx_agg_cfg_v2(struct rtw89_dev *rtwdev)
        rtw89_write32(rtwdev, R_AX_RXAGG_1_V1, 0x1F);
 }
 
+static void rtw89_usb_rx_agg_cfg_v3(struct rtw89_dev *rtwdev)
+{
+       const u32 rxagg_0 = FIELD_PREP_CONST(B_BE_RXAGG_0_EN, 1) |
+                           FIELD_PREP_CONST(B_BE_RXAGG_0_NUM_TH, 255) |
+                           FIELD_PREP_CONST(B_BE_RXAGG_0_TIME_32US_TH, 32) |
+                           FIELD_PREP_CONST(B_BE_RXAGG_0_BUF_SZ_1K, 20);
+
+       rtw89_write32(rtwdev, R_BE_RXAGG_0_V1, rxagg_0);
+       rtw89_write32(rtwdev, R_BE_RXAGG_1_V1, 0x1F);
+}
+
 static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
 {
        switch (rtwdev->chip->chip_id) {
@@ -814,6 +825,9 @@ static void rtw89_usb_rx_agg_cfg(struct rtw89_dev *rtwdev)
        case RTL8852C:
                rtw89_usb_rx_agg_cfg_v2(rtwdev);
                break;
+       case RTL8922A:
+               rtw89_usb_rx_agg_cfg_v3(rtwdev);
+               break;
        default:
                rtw89_warn(rtwdev, "%s: USB RX agg not support\n", __func__);
                return;
index 82de700eb1428355881bea93865bd6bf0be06156..bdf3125597438b5f9defd700c101bf0708e8d280 100644 (file)
 
 #define R_AX_RXAGG_1_V1                        0x6004
 
+#define R_BE_RXAGG_0_V1                        0x6000
+#define B_BE_RXAGG_0_EN                        BIT(31)
+#define B_BE_RXAGG_0_NUM_TH            GENMASK(23, 16)
+#define B_BE_RXAGG_0_TIME_32US_TH      GENMASK(15, 8)
+#define B_BE_RXAGG_0_BUF_SZ_1K         GENMASK(7, 0)
+
+#define R_BE_RXAGG_1_V1                        0x6004
+
 #define R_AX_RXAGG_0                   0x8900
 #define B_AX_RXAGG_0_BUF_SZ_4K         GENMASK(7, 0)