#include "iris_core.h"
#include "iris_firmware.h"
+#define IRIS_PAS_ID 9
+
#define MAX_FIRMWARE_NAME_SIZE 128
static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
{
- u32 pas_id = core->iris_platform_data->pas_id;
const struct firmware *firmware = NULL;
struct device *dev = core->dev;
struct resource res;
}
ret = qcom_mdt_load(dev, firmware, fw_name,
- pas_id, mem_virt, mem_phys, res_size, NULL);
+ IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL);
memunmap(mem_virt);
err_release_fw:
return -ENOMEM;
}
- ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
+ ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID);
if (ret) {
dev_err(core->dev, "auth and reset failed: %d\n", ret);
return ret;
cp_config->cp_nonpixel_size);
if (ret) {
dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ qcom_scm_pas_shutdown(IRIS_PAS_ID);
return ret;
}
}
int iris_fw_unload(struct iris_core *core)
{
- return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ return qcom_scm_pas_shutdown(IRIS_PAS_ID);
}
int iris_set_hw_state(struct iris_core *core, bool resume)
struct iris_core;
struct iris_inst;
-#define IRIS_PAS_ID 9
#define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */
#define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */
unsigned int controller_rst_tbl_size;
u64 dma_mask;
const char *fwname;
- u32 pas_id;
struct iris_fmt *inst_iris_fmts;
u32 inst_iris_fmts_size;
struct platform_inst_caps *inst_caps;
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu-1.0/venus.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8250_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
.inst_caps = &platform_inst_cap_sm8250,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu20_p1.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8250_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
.inst_caps = &platform_inst_cap_sm8250,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu33_p4.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu35_p4.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_sm8550,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
- .pas_id = IRIS_PAS_ID,
.inst_iris_fmts = platform_fmts_sm8550_dec,
.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
.inst_caps = &platform_inst_cap_qcs8300,