drm/amd/display: bypass post csc for additional color spaces in dcn42

[Why]
This aligns dcn42 with:
"drm/amd/display: bypass post csc for additional color spaces in dal"

[How]
Apply the same post csc bypass logic to dcn42 dpp using the
helper function.

Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Chenyu Chen <chen-yu.chen@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
index c126fb9d5bfa9a03f93ffd454aa61b925748c3b8..b5d7ed5dd511ce23ad3ed2e0136094ae5b26d959 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
@@ -269,10 +269,10 @@ static void dpp42_dpp_setup(
 
                tbl_entry.color_space = input_color_space;
 
-               if (color_space >= COLOR_SPACE_YCBCR601)
-                       select = INPUT_CSC_SELECT_ICSC;
-               else
+               if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
                        select = INPUT_CSC_SELECT_BYPASS;
+               else
+                       select = INPUT_CSC_SELECT_ICSC;
 
                dpp3_program_post_csc(dpp_base, color_space, select,
                        &tbl_entry);