ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1)

ENET1 is currently disabled and not supported/working on the concerto EVK.
Add support for this optional configuration in a separate dtsi, so that it
can be selectively enabled/disabled.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index af9b92f7709b438a150d1ec5f9c1ab2a2dec72c2..70d19eccddb4ce02f6733578e82427b8f8fdf6a6 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
@@ -44,57 +44,7 @@
        assigned-clock-rates = <786432000>;
 };
 
-&fec1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
-       phy-mode = "rmii";
-       phy-handle = <&ethphy0>;
-       status = "okay";
-
-       mdio {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               ethphy0: ethernet-phy@1 {
-                       compatible = "ethernet-phy-ieee802.3-c22";
-                       reg = <1>;
-                       clocks = <&rmii_ref_clk>;
-                       clock-names = "rmii-ref";
-                       reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
-                       reset-assert-us = <100000>;
-                       micrel,led-mode = <1>;
-                       micrel,rmii-reference-clock-select-25-mhz;
-               };
-       };
-};
-
 &iomuxc {
-       pinctrl_enet1: enet1grp {
-               fsl,pins = <
-                       MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
-                       MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
-                       MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
-                       MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
-                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
-               >;
-       };
-
-       pinctrl_enet1_gpio: enet1-gpiogrp {
-               fsl,pins = <
-                       MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x1b0b0 /* fec1 reset */
-               >;
-       };
-
-       pinctrl_enet1_mdio: enet1-mdiogrp {
-               fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
-                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
-               >;
-       };
-
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6UL_PAD_CSI_PIXCLK__I2C1_SCL          0x4001b8b0

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
index fead54ac8c6b97c9e8cfd168bf336a0ac09828f6..f099ca5d0e8f0b6a3ff9e7542720ca7336657291 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
@@ -52,10 +52,6 @@
        status = "okay";
 };
 
-&fec1 {
-       status = "disabled";
-};
-
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
index 3905171b47b321b9784122aea1eadb4ee93bdd8c..b5e6a3306e1cd64e5422b216bc2be76066aba9f5 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-enet1.dtsi"
 
 / {
        model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
new file mode 100644 (file)
index 0000000..6b1e343
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
+ * the EC configuration option ((ethernet PHY assembled on SOM).
+ *
+ * Copyright 2019-2024 Variscite Ltd.
+ * Copyright 2026 Dimonoff
+ */
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_enet1: enet1grp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+               >;
+       };
+};
+
+&mdio_enet2 {
+       ethphy0: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+               clocks = <&rmii_ref_clk>;
+               clock-names = "rmii-ref";
+               reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <100000>;
+               micrel,led-mode = <1>;
+               micrel,rmii-reference-clock-select-25-mhz;
+       };
+};

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
index 334ed3bbe02cec0db55c162233652ddcd6b697e4..b29fcdc079e37568ced957a1e8869f60a3f1652d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
@@ -26,6 +26,17 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               ethphy0: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+                       clocks = <&rmii_ref_clk>;
+                       clock-names = "rmii-ref";
+                       reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <100000>;
+                       micrel,led-mode = <1>;
+                       micrel,rmii-reference-clock-select-25-mhz;
+               };
+
                ethphy1: ethernet-phy@3 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <3>;

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index b4e6a9316dd81481ab56216b178c71e8d7a98f05..feea24c0e0683dae81042ffc6b6c247f9b6e3ff7 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
@@ -29,4 +29,10 @@
                        MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x1b0b0 /* WL_REG_ON (WIFI_EN) */
                >;
        };
+
+       pinctrl_enet1_gpio: enet1-gpiogrp {
+               fsl,pins = <
+                       MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x1b0b0 /* fec1 reset */
+               >;
+       };
 };

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
index 89b6032203a28e13680438cf92b9eb08ac8333ec..86f558c76fb3e3c3871b9177cd12f2f5fe524e74 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
@@ -12,6 +12,7 @@
 #include "imx6ul-var-som-concerto-common.dtsi"
 #include "imx6ul-var-som-wifi.dtsi"
 #include "imx6ul-var-som-enet2.dtsi"
+#include "imx6ul-var-som-enet1.dtsi"
 
 / {
        model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
index 3067ff6a1bc7486b94ff9f9fed4d1840208b85aa..f120b1dca75ce7a05002517aa49d456f3904583d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
@@ -27,4 +27,10 @@
                        MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x1b0b0 /* WL_REG_ON (WIFI_EN) */
                >;
        };
+
+       pinctrl_enet1_gpio: enet1-gpiogrp {
+               fsl,pins = <
+                       MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0 /* fec1 reset */
+               >;
+       };
 };