clk: renesas: r9a09g077: Add MTU3 module clock

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a MTU3
block connected to the PCLKH and with a module clock controlled by
register 0x308, bit 0.

Add support for the module clock.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260410163530.383818-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 93b15e06a19bcfdeda16d79ee532ea9df7a0b2db..f777601a23b93965b2bf156bf3e45ae09066f37b 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
        DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
        DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
        DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
+       DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH),
        DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
        DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
        DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),