]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: imx93-11x11-evk: change usdhc tuning step for eMMC and SD
authorLuke Wang <ziniu.wang_1@nxp.com>
Tue, 3 Feb 2026 11:23:09 +0000 (19:23 +0800)
committerFrank Li <Frank.Li@nxp.com>
Tue, 24 Feb 2026 23:12:12 +0000 (18:12 -0500)
During system resume, the following errors occurred:

  [  430.638625] mmc1: error -84 writing Cache Enable bit
  [  430.643618] mmc1: error -84 doing runtime resume

For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a wrong delay cell near the gap to be selected.

Set the tuning step to 1 to avoid selecting the wrong delay cell.

For SDIO, the gap is sufficiently large, so the default tuning step does
not cause this issue.

Fixes: e37907bd8294 ("arm64: dts: freescale: add i.MX93 11x11 EVK basic support")
Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi

index 301e9f05122ebc2bd41f0374be17bd88a2dfce75..7d3fc4ad7b8b7cf213e8ec977589509a7419a04b 100644 (file)
        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        bus-width = <8>;
        non-removable;
+       fsl,tuning-step = <1>;
        status = "okay";
 };
 
        cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
        vmmc-supply = <&reg_usdhc2_vmmc>;
        bus-width = <4>;
+       fsl,tuning-step = <1>;
        status = "okay";
        no-mmc;
 };