arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC

Add the base USB devicetree definitions for Kaanapali platform. The overall
chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
(rev. v8) and M31 eUSB2 PHY.

Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260406174613.3388987-2-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1aab459bcdfd7f6eabd6ec3b090e03..bab654bbd6d041639dbb286342ff06e915d9fcb0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -3138,6 +3138,77 @@
                        };
                };
 
+               usb_hsphy: phy@88e3000 {
+                       compatible = "qcom,kaanapali-m31-eusb2-phy",
+                                    "qcom,sm8750-m31-eusb2-phy";
+                       reg = <0x0 0x88e3000 0x0 0x29c>;
+
+                       clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+                       clock-names = "ref";
+
+                       resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               usb_dp_qmpphy: phy@88e8000 {
+                       compatible = "qcom,kaanapali-qmp-usb3-dp-phy",
+                                    "qcom,sm8750-qmp-usb3-dp-phy";
+                       reg = <0x0 0x088e8000 0x0 0x4000>;
+
+                       clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+                                <&tcsr TCSR_USB3_CLKREF_EN>,
+                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+                                <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "ref",
+                                     "com_aux",
+                                     "usb3_pipe";
+
+                       resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+                                <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+                       reset-names = "phy",
+                                     "common";
+
+                       power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+                       #clock-cells = <1>;
+                       #phy-cells = <1>;
+
+                       orientation-switch;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_dp_qmpphy_out: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       usb_dp_qmpphy_usb_ss_in: endpoint {
+                                               remote-endpoint = <&usb_dwc3_ss>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       usb_dp_qmpphy_dp_in: endpoint {
+                                       };
+                               };
+                       };
+               };
+
                camcc: clock-controller@956d000 {
                        compatible = "qcom,kaanapali-camcc";
                        reg = <0x0 0x0956d000 0x0 0x80000>;
@@ -3422,6 +3493,89 @@
                        #reset-cells = <1>;
                };
 
+               usb: usb@a600000 {
+                       compatible = "qcom,kaanapali-dwc3", "qcom,snps-dwc3";
+                       reg = <0x0 0x0a600000 0x0 0xfc100>;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+                       clock-names = "cfg_noc",
+                                     "core",
+                                     "iface",
+                                     "sleep",
+                                     "mock_utmi";
+
+                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "dwc_usb3",
+                                         "pwr_event",
+                                         "hs_phy_irq",
+                                         "dp_hs_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "ss_phy_irq";
+
+                       power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+                       interconnects = <&aggre_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_USB3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "usb-ddr", "apps-usb";
+                       iommus = <&apps_smmu 0x40 0x0>;
+
+                       phys = <&usb_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+                       phy-names = "usb2-phy", "usb3-phy";
+
+                       snps,hird-threshold = /bits/ 8 <0x0>;
+                       snps,usb2-gadget-lpm-disable;
+                       snps,dis_u2_susphy_quirk;
+                       snps,dis_enblslpm_quirk;
+                       snps,dis-u1-entry-quirk;
+                       snps,dis-u2-entry-quirk;
+                       snps,is-utmi-l1-suspend;
+                       snps,usb3_lpm_capable;
+                       snps,usb2-lpm-disable;
+                       snps,has-lpm-erratum;
+                       tx-fifo-resize;
+                       dma-coherent;
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_dwc3_hs: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       usb_dwc3_ss: endpoint {
+                                               remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+                                       };
+                               };
+                       };
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,kaanapali-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x10000>,