drm/amdgpu/gfx12: align mqd settings with KFD

Make sure to set the quantum bits in the compute MQD
for better fairness across queues of the same priority.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 65c33823a688fcbc4ad2d9b82312f35ea0cad6b1..60f0c7d6a7a3744645d9d36603e4b5c3337fc178 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3268,6 +3268,11 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
        mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
 
+       tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+       tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+       tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+       mqd->cp_hqd_quantum = tmp;
+
        mqd->cp_hqd_active = prop->hqd_active;
 
        /* set UQ fenceaddress */