arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings

Correct the unit address of cache controller and SRAM nodes in Qualcomm
Glymur SoC DTSI to fix W=1 DTC warnings:

  glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000"
  glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600"

Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 3389103408b610deee9ca4227c1b1f4f9a1469f2..0c5cb8532b202c29ea5fca6e65e714ef5b09555e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -5873,7 +5873,7 @@
                        #interconnect-cells = <2>;
                };
 
-               system-cache-controller@20400000 {
+               system-cache-controller@21800000 {
                        compatible = "qcom,glymur-llcc";
                        reg = <0x0 0x21800000 0x0 0x100000>,
                              <0x0 0x21a00000 0x0 0x100000>,
@@ -5914,7 +5914,7 @@
                        #interconnect-cells = <2>;
                };
 
-               imem: sram@81e08000 {
+               imem: sram@81e08600 {
                        compatible = "mmio-sram";
                        reg = <0x0 0x81e08600 0x0 0x300>;