arm64: dts: qcom: sm8750: Add camera clock controller

The camera clock controller is split into cambistmclk and camcc. The
cambist clock controller handles the mclks and the rest of the clocks of
camera are part of the camcc clock controller.
Add the camcc clock controller device node for SM8750 SoC.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com
[bjorn: Fixed include file order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 5921f83aafacb7ee728f335c3ed346614e0b0db6..49d4a9a34c04bb832c3aa99b82efb309e876674c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -5,6 +5,8 @@
 
 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h>
+#include <dt-bindings/clock/qcom,sm8750-camcc.h>
 #include <dt-bindings/clock/qcom,sm8750-dispcc.h>
 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
@@ -2082,6 +2084,23 @@
                        clocks = <&rpmhcc RPMH_IPA_CLK>;
                };
 
+               cambistmclkcc: clock-controller@1760000 {
+                      compatible = "qcom,sm8750-cambistmclkcc";
+                      reg = <0x0 0x1760000 0x0 0x6000>;
+                      clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
+                               <&bi_tcxo_div2>,
+                               <&bi_tcxo_ao_div2>,
+                               <&sleep_clk>;
+                       power-domains = <&rpmhpd RPMHPD_MMCX>,
+                                       <&rpmhpd RPMHPD_MX>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                mmss_noc: interconnect@1780000 {
                        compatible = "qcom,sm8750-mmss-noc";
                        reg = <0x0 0x01780000 0x0 0x5b800>;
@@ -3444,6 +3463,23 @@
                        #power-domain-cells = <1>;
                };
 
+               camcc: clock-controller@ade0000 {
+                       compatible = "qcom,sm8750-camcc";
+                       reg = <0x0 0xade0000 0x0 0x20000>;
+                       clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+                                <&bi_tcxo_div2>,
+                                <&bi_tcxo_ao_div2>,
+                                <&sleep_clk>;
+                       power-domains = <&rpmhpd RPMHPD_MMCX>,
+                                       <&rpmhpd RPMHPD_MXC>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8750-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;