arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs

The eDP PHY nodes on lemans were missing the reference clock voting.
This initially went unnoticed because the clock was implicitly enabled
by the UFS PHY driver, and the eDP PHY happened to rely on that.

After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off
calls"), the UFS driver no longer keeps the reference clock enabled.
As a result, the eDP PHY fails to power on.

To fix this, add eDP reference clock for eDP PHYs on lemans chipset
ensuring reference clock is enabled.

Fixes: e1e3e5673f8d7 ("arm64: dts: qcom: sa8775p: add DisplayPort device nodes")
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260128114853.2543416-3-quic_riteshk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index dffbe1f5250adfdc4141f3f9b0fec30e48480fa4..522ba43836a2425a8612506f5f7113f291f34706 100644 (file)
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5658,9 +5658,11 @@
                                      <0x0 0x0aec2000 0x0 0x1c8>;
 
                                clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
-                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_EDP_REF_CLKREF_EN>;
                                clock-names = "aux",
-                                             "cfg_ahb";
+                                             "cfg_ahb",
+                                             "ref";
 
                                #clock-cells = <1>;
                                #phy-cells = <0>;
@@ -5677,9 +5679,11 @@
                                      <0x0 0x0aec5000 0x0 0x1c8>;
 
                                clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
-                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+                                        <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_EDP_REF_CLKREF_EN>;
                                clock-names = "aux",
-                                             "cfg_ahb";
+                                             "cfg_ahb",
+                                             "ref";
 
                                #clock-cells = <1>;
                                #phy-cells = <0>;