#define SIM1_BASE_ADDR 0x29290000
-#define WDG3_RBASE 0x292a0000UL
-
#define SIM_SEC_BASE_ADDR 0x2802B000
#define CGC1_SOSCDIV_ADDR 0x292C0108
#define ANATOP_BASE_ADDR 0x44480000UL
-#ifdef CONFIG_IMX94
-#define WDG3_BASE_ADDR 0x49220000UL
-#define WDG4_BASE_ADDR 0x49230000UL
-#else
-#define WDG3_BASE_ADDR 0x42490000UL
-#define WDG4_BASE_ADDR 0x424a0000UL
-#endif
-#define WDG5_BASE_ADDR 0x424b0000UL
-
#define GPIO2_BASE_ADDR 0x43810000UL
#define GPIO3_BASE_ADDR 0x43820000UL
#define GPIO4_BASE_ADDR 0x43840000UL
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_RBASE
#endif
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define CFG_SYS_FSL_USDHC_NUM 2
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */
#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB (Totally 16GB) */
#endif
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif
#define CFG_MXC_USB_FLAGS 0
#endif
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif /* __KONTRON_MX93_CONFIG_H */
#include "imx7ulp_spl.h"
#endif
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG1_RBASE
-
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
/* UART */
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG1_RBASE
-
#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
/* UART */
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif /* __PHYCORE_IMX91_93_H */
#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M)
#define PHYS_SDRAM_2_SIZE SZ_6G
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
#endif