]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
imx: Remove hardcoded watchdog base address macros
authorAlice Guo <alice.guo@nxp.com>
Tue, 19 May 2026 06:22:08 +0000 (14:22 +0800)
committerFabio Estevam <festevam@gmail.com>
Fri, 5 Jun 2026 11:58:00 +0000 (08:58 -0300)
The watchdog base addresses are now obtained from the devicetree via
ofnode_* functions. Remove the hardcoded macro definitions as they are
no longer needed.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
16 files changed:
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
arch/arm/include/asm/arch-imx9/imx-regs.h
include/configs/imx8ulp_evk.h
include/configs/imx91_evk.h
include/configs/imx91_frdm.h
include/configs/imx93_evk.h
include/configs/imx93_frdm.h
include/configs/imx93_qsb.h
include/configs/imx93_var_som.h
include/configs/imx94_evk.h
include/configs/imx95_evk.h
include/configs/kontron-osm-s-mx93.h
include/configs/mx7ulp_com.h
include/configs/mx7ulp_evk.h
include/configs/phycore_imx91_93.h
include/configs/toradex-smarc-imx95.h

index a038cc1df3346b1e6d417747be4eb384e844b541..f9c5e21c14f73e7e570a6420d0d3781971136531 100644 (file)
@@ -20,8 +20,6 @@
 
 #define SIM1_BASE_ADDR         0x29290000
 
-#define WDG3_RBASE             0x292a0000UL
-
 #define SIM_SEC_BASE_ADDR      0x2802B000
 
 #define CGC1_SOSCDIV_ADDR      0x292C0108
index 2d084e5227ab2fe6f24299679f04cc380035ea15..fbf2e6a2b01d137d270add6b522e19ffb58c20e3 100644 (file)
 
 #define ANATOP_BASE_ADDR    0x44480000UL
 
-#ifdef CONFIG_IMX94
-#define WDG3_BASE_ADDR      0x49220000UL
-#define WDG4_BASE_ADDR      0x49230000UL
-#else
-#define WDG3_BASE_ADDR      0x42490000UL
-#define WDG4_BASE_ADDR      0x424a0000UL
-#endif
-#define WDG5_BASE_ADDR      0x424b0000UL
-
 #define GPIO2_BASE_ADDR            0x43810000UL
 #define GPIO3_BASE_ADDR            0x43820000UL
 #define GPIO4_BASE_ADDR            0x43840000UL
index edfd6f70815645957f676b0fc03b38bd72791946..b4f80fb944b7e4252d7c9631c7c79347a3153312 100644 (file)
@@ -30,6 +30,4 @@
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR                 WDG3_RBASE
 #endif
index 9c5014fd0a5fe0344c3b5354531fe16a3149c514..13918e2b873bb00a460fce1f5dee2a379b54c355 100644 (file)
@@ -16,6 +16,4 @@
 #define PHYS_SDRAM             0x80000000
 #define PHYS_SDRAM_SIZE                0x80000000 /* 2GB DDR */
 
-#define WDOG_BASE_ADDR         WDG3_BASE_ADDR
-
 #endif
index 6d051ed88a5a38c0227e070fb008b501acbb3fa1..480b3fb477a57531fc896deae7cd264bf62bc5c1 100644 (file)
@@ -20,6 +20,4 @@
 #define PHYS_SDRAM             0x80000000
 #define PHYS_SDRAM_SIZE                SZ_2G /* 2GB DDR */
 
-#define WDOG_BASE_ADDR         WDG3_BASE_ADDR
-
 #endif
index ffd72a38bcbb476ee71fcc910bf3f9ff3fa9c60b..67774f547906720393a523fa8ad199d0c32fa05b 100644 (file)
@@ -26,7 +26,4 @@
 #define PHYS_SDRAM                      0x80000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
-
 #endif
index c98c10774cb77cdaee5e7882cfebd1b8e8c72a85..bcea360b399d5785dd8fb7f3a281796f90bb536a 100644 (file)
@@ -20,7 +20,4 @@
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR                 WDG3_BASE_ADDR
-
 #endif
index a7b94f7ab57406c6ecaffa873a702edc53cc430f..350f094c2a60a6212e6890e99767dbe6e3b3ba9e 100644 (file)
@@ -16,6 +16,4 @@
 #define PHYS_SDRAM             0x80000000
 #define PHYS_SDRAM_SIZE                0x80000000 /* 2GB DDR */
 
-#define WDOG_BASE_ADDR         WDG3_BASE_ADDR
-
 #endif
index 9dc10aea407f80312348d624b687f1c06faceb83..6a425e6d1ea3e077f663e2343624b8a879c060da 100644 (file)
@@ -38,7 +38,4 @@
 
 #define CFG_SYS_FSL_USDHC_NUM 2
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
-
 #endif
index f93c3c4e4a8b75eb721dc2efdf55d909e8904255..2623c13db06a24bd1c8ae41b8c5f710d62fc553b 100644 (file)
@@ -18,7 +18,4 @@
 #define PHYS_SDRAM_SIZE                             0x70000000UL /* 2GB  - 256MB DDR */
 #define PHYS_SDRAM_2_SIZE                   0x180000000 /* 8GB */
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
-
 #endif
index 3d22740b3f4377608ff546b5d0441a1660b5e564..1fdc9ce21efd1c4128d8a3f85af4d80c283bd454 100644 (file)
@@ -23,6 +23,4 @@
 #define PHYS_SDRAM_2_SIZE              0x380000000 /* 14GB (Totally 16GB) */
 #endif
 
-#define WDOG_BASE_ADDR                 WDG3_BASE_ADDR
-
 #endif
index ab2b42298c89fc47ba4b68a89e6cd8cbec7230fc..fed75e6fa12a1464bfda2dce84309d5e62000cfb 100644 (file)
@@ -25,6 +25,4 @@
 #define CFG_MXC_USB_FLAGS              0
 #endif
 
-#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
-
 #endif /* __KONTRON_MX93_CONFIG_H */
index d27e9d2eaa144a5a2c02afd8da6053fb751eb16e..501c3059cc3c998f60429089bea78917aef20fb4 100644 (file)
@@ -15,9 +15,6 @@
 #include "imx7ulp_spl.h"
 #endif
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR                 WDG1_RBASE
-
 #define CFG_SYS_HZ_CLOCK               1000000 /* Fixed at 1MHz from TSTMR */
 
 /* UART */
index ace1eee70cf62192733aaa46fce826fe48d95f4c..21dbec837f0903947adbd60903daee89902e2254 100644 (file)
@@ -11,9 +11,6 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR                 WDG1_RBASE
-
 #define CFG_SYS_HZ_CLOCK               1000000 /* Fixed at 1Mhz from TSTMR */
 
 /* UART */
index 02fa1d9b274d1f5cc95b1578d7c899fb61dfba90..d1bf086546f2d21a377314a891b4d2b6ff734488 100644 (file)
@@ -22,7 +22,4 @@
 #define PHYS_SDRAM                   0x80000000
 #define PHYS_SDRAM_SIZE              0x80000000
 
-/* Using ULP WDOG for reset */
-#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
-
 #endif /* __PHYCORE_IMX91_93_H */
index e1aebd70af2d52c3c4b08ee100f6ccb186b5571a..8a880b9650389224f1f690c9d9e82d6ca4279b2d 100644 (file)
@@ -19,6 +19,4 @@
 #define PHYS_SDRAM_SIZE                (SZ_2G - SZ_256M)
 #define PHYS_SDRAM_2_SIZE      SZ_6G
 
-#define WDOG_BASE_ADDR WDG3_BASE_ADDR
-
 #endif