iris_ctrls.o \
iris_firmware.o \
iris_hfi_common.o \
+ iris_hfi_gen1.o \
iris_hfi_gen1_command.o \
iris_hfi_gen1_response.o \
+ iris_hfi_gen2.o \
iris_hfi_gen2_command.o \
iris_hfi_gen2_packet.o \
iris_hfi_gen2_response.o \
iris_hfi_queue.o \
- iris_platform_gen1.o \
- iris_platform_gen2.o \
+ iris_platform_vpu2.o \
+ iris_platform_vpu3x.o \
iris_power.o \
iris_probe.o \
iris_resources.o \
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
-#include "iris_core.h"
#include "iris_ctrls.h"
#include "iris_platform_common.h"
-#include "iris_resources.h"
#include "iris_hfi_gen1.h"
#include "iris_hfi_gen1_defines.h"
#include "iris_vpu_buffer.h"
-#include "iris_vpu_common.h"
-#include "iris_instance.h"
-
-#include "iris_platform_sc7280.h"
#define BITRATE_MIN 32000
#define BITRATE_MAX 160000000
-#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2)
#define BITRATE_STEP 100
-static struct iris_fmt platform_fmts_sm8250_dec[] = {
- [IRIS_FMT_H264] = {
- .pixfmt = V4L2_PIX_FMT_H264,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
- [IRIS_FMT_HEVC] = {
- .pixfmt = V4L2_PIX_FMT_HEVC,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
- [IRIS_FMT_VP9] = {
- .pixfmt = V4L2_PIX_FMT_VP9,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
-};
-
static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
{
.cap_id = PIPE,
},
};
-static struct platform_inst_caps platform_inst_cap_sm8250 = {
- .min_frame_width = 128,
- .max_frame_width = 8192,
- .min_frame_height = 128,
- .max_frame_height = 8192,
- .max_mbpf = 138240,
- .mb_cycles_vsp = 25,
- .mb_cycles_vpp = 200,
- .max_frame_rate = MAXIMUM_FPS,
- .max_operating_rate = MAXIMUM_FPS,
-};
-
-static const struct icc_info sm8250_icc_table[] = {
- { "cpu-cfg", 1000, 1000 },
- { "video-mem", 1000, 15000000 },
-};
-
-static const char * const sm8250_clk_reset_table[] = { "bus", "core" };
-
-static const struct bw_info sm8250_bw_table_dec[] = {
- { ((4096 * 2160) / 256) * 60, 2403000 },
- { ((4096 * 2160) / 256) * 30, 1224000 },
- { ((1920 * 1080) / 256) * 60, 812000 },
- { ((1920 * 1080) / 256) * 30, 416000 },
-};
-
-static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
-
-static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" };
-
-static const struct platform_clk_data sm8250_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
-};
-
-static const char * const sm8250_opp_clk_table[] = {
- "vcodec0_core",
- NULL,
-};
-
-static const struct tz_cp_config tz_cp_config_sm8250[] = {
- {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
- },
-};
-
static const u32 sm8250_vdec_input_config_param_default[] = {
HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE,
HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT,
.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
};
-
-const struct iris_platform_data sm8250_data = {
- .firmware_data = &iris_hfi_gen1_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
- .vpu_ops = &iris_vpu2_ops,
- .icc_tbl = sm8250_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
- .clk_rst_tbl = sm8250_clk_reset_table,
- .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),
- .bw_tbl_dec = sm8250_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
- .pmdomain_tbl = sm8250_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
- .opp_pd_tbl = sm8250_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
- .clk_tbl = sm8250_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
- .opp_clk_tbl = sm8250_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu-1.0/venus.mbn",
- .inst_iris_fmts = platform_fmts_sm8250_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
- .inst_caps = &platform_inst_cap_sm8250,
- .tz_cp_config_data = tz_cp_config_sm8250,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
- .num_vpp_pipe = 4,
- .max_session_count = 16,
- .max_core_mbpf = NUM_MBS_8K,
- .max_core_mbps = ((7680 * 4320) / 256) * 60,
-};
-
-const struct iris_platform_data sc7280_data = {
- .firmware_data = &iris_hfi_gen1_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
- .vpu_ops = &iris_vpu2_ops,
- .icc_tbl = sm8250_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
- .bw_tbl_dec = sc7280_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
- .pmdomain_tbl = sm8250_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
- .opp_pd_tbl = sc7280_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
- .clk_tbl = sc7280_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
- .opp_clk_tbl = sc7280_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu20_p1.mbn",
- .inst_iris_fmts = platform_fmts_sm8250_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
- .inst_caps = &platform_inst_cap_sm8250,
- .tz_cp_config_data = tz_cp_config_sm8250,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
- .num_vpp_pipe = 1,
- .no_aon = true,
- .max_session_count = 16,
- .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
- /* max spec for SC7280 is 4096x2176@60fps */
- .max_core_mbps = 4096 * 2176 / 256 * 60,
-};
* Copyright (c) 2025 Linaro Ltd
*/
-#include "iris_core.h"
#include "iris_ctrls.h"
#include "iris_hfi_gen2.h"
#include "iris_hfi_gen2_defines.h"
#include "iris_platform_common.h"
#include "iris_vpu_buffer.h"
-#include "iris_vpu_common.h"
-
-#include "iris_platform_qcs8300.h"
-#include "iris_platform_sm8650.h"
-#include "iris_platform_sm8750.h"
#define VIDEO_ARCH_LX 1
#define BITRATE_MAX 245000000
-static struct iris_fmt platform_fmts_sm8550_dec[] = {
- [IRIS_FMT_H264] = {
- .pixfmt = V4L2_PIX_FMT_H264,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
- [IRIS_FMT_HEVC] = {
- .pixfmt = V4L2_PIX_FMT_HEVC,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
- [IRIS_FMT_VP9] = {
- .pixfmt = V4L2_PIX_FMT_VP9,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
- [IRIS_FMT_AV1] = {
- .pixfmt = V4L2_PIX_FMT_AV1,
- .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
- },
-};
-
static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
{
.cap_id = PROFILE_H264,
},
};
-static struct platform_inst_caps platform_inst_cap_sm8550 = {
- .min_frame_width = 96,
- .max_frame_width = 8192,
- .min_frame_height = 96,
- .max_frame_height = 8192,
- .max_mbpf = (8192 * 4352) / 256,
- .mb_cycles_vpp = 200,
- .mb_cycles_fw = 489583,
- .mb_cycles_fw_vpp = 66234,
- .num_comv = 0,
- .max_frame_rate = MAXIMUM_FPS,
- .max_operating_rate = MAXIMUM_FPS,
-};
-
-static const struct icc_info sm8550_icc_table[] = {
- { "cpu-cfg", 1000, 1000 },
- { "video-mem", 1000, 15000000 },
-};
-
-static const char * const sm8550_clk_reset_table[] = { "bus" };
-
-static const struct bw_info sm8550_bw_table_dec[] = {
- { ((4096 * 2160) / 256) * 60, 1608000 },
- { ((4096 * 2160) / 256) * 30, 826000 },
- { ((1920 * 1080) / 256) * 60, 567000 },
- { ((1920 * 1080) / 256) * 30, 294000 },
-};
-
-static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
-
-static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
-
-static const struct platform_clk_data sm8550_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
-};
-
-static const char * const sm8550_opp_clk_table[] = {
- "vcodec0_core",
- NULL,
-};
-
-static const struct tz_cp_config tz_cp_config_sm8550[] = {
- {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
- },
-};
-
static const u32 sm8550_vdec_input_config_params_default[] = {
HFI_PROP_BITSTREAM_RESOLUTION,
HFI_PROP_CROP_OFFSETS,
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
-
-const struct iris_platform_data sm8550_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
- .vpu_ops = &iris_vpu3_ops,
- .icc_tbl = sm8550_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
- .clk_rst_tbl = sm8550_clk_reset_table,
- .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
- .bw_tbl_dec = sm8550_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
- .opp_pd_tbl = sm8550_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
- .clk_tbl = sm8550_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
- .opp_clk_tbl = sm8550_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu30_p4.mbn",
- .inst_iris_fmts = platform_fmts_sm8550_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
- .inst_caps = &platform_inst_cap_sm8550,
- .tz_cp_config_data = tz_cp_config_sm8550,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
- .num_vpp_pipe = 4,
- .max_session_count = 16,
- .max_core_mbpf = NUM_MBS_8K * 2,
- .max_core_mbps = ((7680 * 4320) / 256) * 60,
-};
-
-/*
- * Shares most of SM8550 data except:
- * - vpu_ops to iris_vpu33_ops
- * - clk_rst_tbl to sm8650_clk_reset_table
- * - controller_rst_tbl to sm8650_controller_reset_table
- * - fwname to "qcom/vpu/vpu33_p4.mbn"
- */
-const struct iris_platform_data sm8650_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu33_buf_size,
- .vpu_ops = &iris_vpu33_ops,
- .icc_tbl = sm8550_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
- .clk_rst_tbl = sm8650_clk_reset_table,
- .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
- .controller_rst_tbl = sm8650_controller_reset_table,
- .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
- .bw_tbl_dec = sm8550_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
- .opp_pd_tbl = sm8550_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
- .clk_tbl = sm8550_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
- .opp_clk_tbl = sm8550_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu33_p4.mbn",
- .inst_iris_fmts = platform_fmts_sm8550_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
- .inst_caps = &platform_inst_cap_sm8550,
- .tz_cp_config_data = tz_cp_config_sm8550,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
- .num_vpp_pipe = 4,
- .max_session_count = 16,
- .max_core_mbpf = NUM_MBS_8K * 2,
- .max_core_mbps = ((7680 * 4320) / 256) * 60,
-};
-
-const struct iris_platform_data sm8750_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu33_buf_size,
- .vpu_ops = &iris_vpu35_ops,
- .icc_tbl = sm8550_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
- .clk_rst_tbl = sm8750_clk_reset_table,
- .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
- .bw_tbl_dec = sm8550_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
- .opp_pd_tbl = sm8550_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
- .clk_tbl = sm8750_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
- .opp_clk_tbl = sm8550_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu35_p4.mbn",
- .inst_iris_fmts = platform_fmts_sm8550_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
- .inst_caps = &platform_inst_cap_sm8550,
- .tz_cp_config_data = tz_cp_config_sm8550,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
- .num_vpp_pipe = 4,
- .max_session_count = 16,
- .max_core_mbpf = NUM_MBS_8K * 2,
- .max_core_mbps = ((7680 * 4320) / 256) * 60,
-};
-
-/*
- * Shares most of SM8550 data except:
- * - inst_caps to platform_inst_cap_qcs8300
- */
-const struct iris_platform_data qcs8300_data = {
- .firmware_data = &iris_hfi_gen2_data,
- .get_vpu_buffer_size = iris_vpu_buf_size,
- .vpu_ops = &iris_vpu3_ops,
- .icc_tbl = sm8550_icc_table,
- .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
- .clk_rst_tbl = sm8550_clk_reset_table,
- .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
- .bw_tbl_dec = sm8550_bw_table_dec,
- .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
- .opp_pd_tbl = sm8550_opp_pd_table,
- .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
- .clk_tbl = sm8550_clk_table,
- .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
- .opp_clk_tbl = sm8550_opp_clk_table,
- /* Upper bound of DMA address range */
- .dma_mask = 0xe0000000 - 1,
- .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
- .inst_iris_fmts = platform_fmts_sm8550_dec,
- .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
- .inst_caps = &platform_inst_cap_qcs8300,
- .tz_cp_config_data = tz_cp_config_sm8550,
- .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
- .num_vpp_pipe = 2,
- .max_session_count = 16,
- .max_core_mbpf = ((4096 * 2176) / 256) * 4,
- .max_core_mbps = (((3840 * 2176) / 256) * 120),
-};
PIPE_4 = 4,
};
+extern const struct iris_firmware_data iris_hfi_gen1_data;
+extern const struct iris_firmware_data iris_hfi_gen2_data;
+
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
extern const struct iris_platform_data sm8250_data;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __IRIS_PLATFORM_SM8250_H__
+#define __IRIS_PLATFORM_SM8250_H__
+
+static const struct bw_info sm8250_bw_table_dec[] = {
+ { ((4096 * 2160) / 256) * 60, 2403000 },
+ { ((4096 * 2160) / 256) * 30, 1224000 },
+ { ((1920 * 1080) / 256) * 60, 812000 },
+ { ((1920 * 1080) / 256) * 30, 416000 },
+};
+
+static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" };
+
+static const struct platform_clk_data sm8250_clk_table[] = {
+ {IRIS_AXI_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_HW_CLK, "vcodec0_core" },
+};
+
+static const char * const sm8250_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_PLATFORM_SM8550_H__
+#define __IRIS_PLATFORM_SM8550_H__
+
+static const char * const sm8550_clk_reset_table[] = { "bus" };
+
+static const struct platform_clk_data sm8550_clk_table[] = {
+ {IRIS_AXI_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_HW_CLK, "vcodec0_core" },
+};
+
+static struct platform_inst_caps platform_inst_cap_sm8550 = {
+ .min_frame_width = 96,
+ .max_frame_width = 8192,
+ .min_frame_height = 96,
+ .max_frame_height = 8192,
+ .max_mbpf = (8192 * 4352) / 256,
+ .mb_cycles_vpp = 200,
+ .mb_cycles_fw = 489583,
+ .mb_cycles_fw_vpp = 66234,
+ .num_comv = 0,
+ .max_frame_rate = MAXIMUM_FPS,
+ .max_operating_rate = MAXIMUM_FPS,
+};
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "iris_core.h"
+#include "iris_ctrls.h"
+#include "iris_platform_common.h"
+#include "iris_resources.h"
+#include "iris_hfi_gen1.h"
+#include "iris_hfi_gen1_defines.h"
+#include "iris_vpu_buffer.h"
+#include "iris_vpu_common.h"
+#include "iris_instance.h"
+
+#include "iris_platform_sc7280.h"
+#include "iris_platform_sm8250.h"
+
+static struct iris_fmt iris_fmts_vpu2_dec[] = {
+ [IRIS_FMT_H264] = {
+ .pixfmt = V4L2_PIX_FMT_H264,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+ [IRIS_FMT_HEVC] = {
+ .pixfmt = V4L2_PIX_FMT_HEVC,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+ [IRIS_FMT_VP9] = {
+ .pixfmt = V4L2_PIX_FMT_VP9,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+};
+
+static struct platform_inst_caps platform_inst_cap_vpu2 = {
+ .min_frame_width = 128,
+ .max_frame_width = 8192,
+ .min_frame_height = 128,
+ .max_frame_height = 8192,
+ .max_mbpf = 138240,
+ .mb_cycles_vsp = 25,
+ .mb_cycles_vpp = 200,
+ .max_frame_rate = MAXIMUM_FPS,
+ .max_operating_rate = MAXIMUM_FPS,
+};
+
+static const struct icc_info iris_icc_info_vpu2[] = {
+ { "cpu-cfg", 1000, 1000 },
+ { "video-mem", 1000, 15000000 },
+};
+
+static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" };
+
+static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" };
+
+static const struct tz_cp_config tz_cp_config_vpu2[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+};
+
+const struct iris_platform_data sc7280_data = {
+ .firmware_data = &iris_hfi_gen1_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu2_ops,
+ .icc_tbl = iris_icc_info_vpu2,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
+ .bw_tbl_dec = sc7280_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
+ .pmdomain_tbl = iris_pmdomain_table_vpu2,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
+ .opp_pd_tbl = sc7280_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
+ .clk_tbl = sc7280_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
+ .opp_clk_tbl = sc7280_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu20_p1.mbn",
+ .inst_iris_fmts = iris_fmts_vpu2_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
+ .inst_caps = &platform_inst_cap_vpu2,
+ .tz_cp_config_data = tz_cp_config_vpu2,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
+ .num_vpp_pipe = 1,
+ .no_aon = true,
+ .max_session_count = 16,
+ .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
+ /* max spec for SC7280 is 4096x2176@60fps */
+ .max_core_mbps = 4096 * 2176 / 256 * 60,
+};
+
+const struct iris_platform_data sm8250_data = {
+ .firmware_data = &iris_hfi_gen1_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu2_ops,
+ .icc_tbl = iris_icc_info_vpu2,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
+ .clk_rst_tbl = iris_clk_reset_table_vpu2,
+ .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2),
+ .bw_tbl_dec = sm8250_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
+ .pmdomain_tbl = iris_pmdomain_table_vpu2,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
+ .opp_pd_tbl = sm8250_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
+ .clk_tbl = sm8250_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
+ .opp_clk_tbl = sm8250_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu-1.0/venus.mbn",
+ .inst_iris_fmts = iris_fmts_vpu2_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
+ .inst_caps = &platform_inst_cap_vpu2,
+ .tz_cp_config_data = tz_cp_config_vpu2,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025 Linaro Ltd
+ */
+
+#include "iris_core.h"
+#include "iris_ctrls.h"
+#include "iris_hfi_gen2.h"
+#include "iris_hfi_gen2_defines.h"
+#include "iris_platform_common.h"
+#include "iris_vpu_buffer.h"
+#include "iris_vpu_common.h"
+
+#include "iris_platform_qcs8300.h"
+#include "iris_platform_sm8550.h"
+#include "iris_platform_sm8650.h"
+#include "iris_platform_sm8750.h"
+
+static struct iris_fmt iris_fmts_vpu3x_dec[] = {
+ [IRIS_FMT_H264] = {
+ .pixfmt = V4L2_PIX_FMT_H264,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+ [IRIS_FMT_HEVC] = {
+ .pixfmt = V4L2_PIX_FMT_HEVC,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+ [IRIS_FMT_VP9] = {
+ .pixfmt = V4L2_PIX_FMT_VP9,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+ [IRIS_FMT_AV1] = {
+ .pixfmt = V4L2_PIX_FMT_AV1,
+ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+ },
+};
+
+static const struct icc_info iris_icc_info_vpu3x[] = {
+ { "cpu-cfg", 1000, 1000 },
+ { "video-mem", 1000, 15000000 },
+};
+
+static const struct bw_info iris_bw_table_dec_vpu3x[] = {
+ { ((4096 * 2160) / 256) * 60, 1608000 },
+ { ((4096 * 2160) / 256) * 30, 826000 },
+ { ((1920 * 1080) / 256) * 60, 567000 },
+ { ((1920 * 1080) / 256) * 30, 294000 },
+};
+
+static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" };
+
+static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" };
+
+static const char * const iris_opp_clk_table_vpu3x[] = {
+ "vcodec0_core",
+ NULL,
+};
+
+static const struct tz_cp_config tz_cp_config_vpu3[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+};
+
+/*
+ * Shares most of SM8550 data except:
+ * - inst_caps to platform_inst_cap_qcs8300
+ */
+const struct iris_platform_data qcs8300_data = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu3_ops,
+ .icc_tbl = iris_icc_info_vpu3x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
+ .clk_rst_tbl = sm8550_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu3x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
+ .pmdomain_tbl = iris_pmdomain_table_vpu3x,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
+ .opp_pd_tbl = iris_opp_pd_table_vpu3x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
+ .clk_tbl = sm8550_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = iris_opp_clk_table_vpu3x,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
+ .inst_iris_fmts = iris_fmts_vpu3x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
+ .inst_caps = &platform_inst_cap_qcs8300,
+ .tz_cp_config_data = tz_cp_config_vpu3,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
+ .num_vpp_pipe = 2,
+ .max_session_count = 16,
+ .max_core_mbpf = ((4096 * 2176) / 256) * 4,
+ .max_core_mbps = (((3840 * 2176) / 256) * 120),
+};
+
+const struct iris_platform_data sm8550_data = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu3_ops,
+ .icc_tbl = iris_icc_info_vpu3x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
+ .clk_rst_tbl = sm8550_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu3x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
+ .pmdomain_tbl = iris_pmdomain_table_vpu3x,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
+ .opp_pd_tbl = iris_opp_pd_table_vpu3x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
+ .clk_tbl = sm8550_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = iris_opp_clk_table_vpu3x,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu30_p4.mbn",
+ .inst_iris_fmts = iris_fmts_vpu3x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .tz_cp_config_data = tz_cp_config_vpu3,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+};
+
+/*
+ * Shares most of SM8550 data except:
+ * - vpu_ops to iris_vpu33_ops
+ * - clk_rst_tbl to sm8650_clk_reset_table
+ * - controller_rst_tbl to sm8650_controller_reset_table
+ * - fwname to "qcom/vpu/vpu33_p4.mbn"
+ */
+const struct iris_platform_data sm8650_data = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .vpu_ops = &iris_vpu33_ops,
+ .icc_tbl = iris_icc_info_vpu3x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
+ .clk_rst_tbl = sm8650_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
+ .controller_rst_tbl = sm8650_controller_reset_table,
+ .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu3x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
+ .pmdomain_tbl = iris_pmdomain_table_vpu3x,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
+ .opp_pd_tbl = iris_opp_pd_table_vpu3x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
+ .clk_tbl = sm8550_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = iris_opp_clk_table_vpu3x,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu33_p4.mbn",
+ .inst_iris_fmts = iris_fmts_vpu3x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .tz_cp_config_data = tz_cp_config_vpu3,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+};
+
+const struct iris_platform_data sm8750_data = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu33_buf_size,
+ .vpu_ops = &iris_vpu35_ops,
+ .icc_tbl = iris_icc_info_vpu3x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
+ .clk_rst_tbl = sm8750_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu3x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
+ .pmdomain_tbl = iris_pmdomain_table_vpu3x,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
+ .opp_pd_tbl = iris_opp_pd_table_vpu3x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
+ .clk_tbl = sm8750_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
+ .opp_clk_tbl = iris_opp_clk_table_vpu3x,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu35_p4.mbn",
+ .inst_iris_fmts = iris_fmts_vpu3x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .tz_cp_config_data = tz_cp_config_vpu3,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((7680 * 4320) / 256) * 60,
+};
projects / thirdparty / linux.git / commitdiff
