struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
- for (k = 0; k < dc->res_pool->pipe_count; k++) {
+ for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream)
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
- for (k = 0; k < dc->res_pool->pipe_count; k++) {
+ for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream ||
*num_steps = 0; // Initialize to 0
// Stream updates
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ for (j = 0; j < (int)dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
{
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
- ASSERT(vlevel < dml->soc.num_states);
+ ASSERT(vlevel < (int)dml->soc.num_states);
/* only pipe 0 is read for voltage and dcf/soc clocks */
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
{
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
- ASSERT(vlevel < dml->soc.num_states);
+ ASSERT(vlevel < (int)dml->soc.num_states);
/* only pipe 0 is read for voltage and dcf/soc clocks */
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
bool result = false;
- int acquired_rmu = 0;
+ uint32_t acquired_rmu = 0;
int mpcc_id_projected = 0;
const struct pwl_params *shaper_lut = NULL;
ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
ASSERT(wb_info->wb_enabled);
ASSERT(wb_info->mpcc_inst >= 0);
- ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
+ ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count);
mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
mcif_buf_params = &wb_info->mcif_buf_params;
}
ASSERT(stream_status);
- ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
+ // Assert non-negative signed capacity first.
+ ASSERT(dc->res_pool->res_cap->num_dwb >= 0);
+ ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb);
/* For each writeback pipe */
for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
enum dc_validate_mode validate_mode)
{
(void)validate_mode;
- int i;
+ unsigned int i;
bool at_least_one_pipe = false;
struct dc_stream_state *stream = NULL;
const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
enum engine_id preferred_engine = link->link_enc->preferred_engine;
/* Store first available for MST second display
* in daisy chain use case
*/
- j = i;
+ j = (int)i;
if (pool->stream_enc[i]->id == preferred_engine)
return pool->stream_enc[i];
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
/* Store first available for MST second display
* in daisy chain use case
*/
- j = i;
+ j = (int)i;
if (pool->stream_enc[i]->id ==
link->link_enc->preferred_engine)
return pool->stream_enc[i];
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
struct dm_pp_clock_levels_with_latency eng_clks = {0};
struct dm_pp_clock_levels_with_latency mem_clks = {0};
struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
- int i;
+ unsigned int i;
unsigned int clk;
unsigned int latency;
/*original logic in dal3*/
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
kfree(pool->base.hw_i2cs[i]);
{
if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
&& caps->max_video_width != 0
- && plane_state->src_rect.width > caps->max_video_width)
+ && plane_state->src_rect.width > 0
+ && (unsigned int)plane_state->src_rect.width > caps->max_video_width)
return DC_FAIL_SURFACE_VALIDATE;
return DC_OK;
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
*/
if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
- j = i;
+ j = (int)i;
if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
link->link_enc->preferred_engine)
static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
{
- int i;
+ unsigned int i;
if (clks->num_levels == 0)
return false;
struct dc *dc,
struct dcn10_resource_pool *pool)
{
- int i;
+ unsigned int i;
int j;
struct dc_context *ctx = dc->ctx;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
struct dc_stream_state *dc_stream)
{
enum dc_status result = DC_OK;
- int i;
+ unsigned int i;
/* Get a DSC if required and available */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
{
enum mmhubbub_wbif_mode wbif_mode;
struct mcif_arb_params *wb_arb_params;
- int i, j, dwb_pipe;
+ int j, dwb_pipe;
+ unsigned int i;
/* Writeback MCIF_WB arbitration parameters */
dwb_pipe = 0;
bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
{
- int i;
+ unsigned int i;
/* Validate DSC config, dsc count validation is already done */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct dc *dc,
struct dc_state *context)
{
- int i;
+ unsigned int i;
/* merge previously split odm pipes since mode support needs to make the decision */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
int *split,
bool *merge)
{
- int i, pipe_idx, vlevel_split;
+ unsigned int i;
+ int pipe_idx, vlevel_split;
int plane_count = 0;
bool force_split = false;
bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
++plane_count;
}
- if (plane_count > dc->res_pool->pipe_count / 2)
+ if ((unsigned int)plane_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
- for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
+ for (vlevel_split = vlevel; (unsigned int)vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
v->ModeSupport[vlevel][0])
break;
/* Impossible to not split this pipe */
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
vlevel = vlevel_split;
else
max_mpc_comb = 0;
bool out = false;
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel;
+ int pipe_cnt, pipe_idx, vlevel;
+ unsigned int i;
ASSERT(pipes);
if (!pipes)
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
ASSERT(pipe_count > 0);
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; (unsigned int)i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
if (!dc->debug.disable_pplib_wm_range) {
struct pp_smu_wm_range_sets ranges = {0};
- int i = 0;
+ int j = 0;
ranges.num_reader_wm_sets = 0;
if (loaded_bb->num_states == 1) {
- ranges.reader_wm_sets[0].wm_inst = (uint8_t)i;
+ ranges.reader_wm_sets[0].wm_inst = (uint8_t)j;
ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.num_reader_wm_sets = 1;
} else if (loaded_bb->num_states > 1) {
- for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
- ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
- ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
- ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ for (j = 0; j < 4 && (unsigned int)j < loaded_bb->num_states; j++) {
+ ranges.reader_wm_sets[j].wm_inst = (uint8_t)j;
+ ranges.reader_wm_sets[j].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[j].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
DC_FP_START();
- dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
+ dcn20_fpu_set_wm_ranges(j, &ranges, loaded_bb);
DC_FP_END();
-
- ranges.num_reader_wm_sets = i + 1;
+ ranges.num_reader_wm_sets = j + 1;
}
ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
goto create_fail;
/* mem input -> ipp -> dpp -> opp -> TG */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; (unsigned int)i < pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; (unsigned int)i < dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 2;
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
bool out = false;
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel;
+ int pipe_cnt, pipe_idx, vlevel;
+ unsigned int i;
ASSERT(pipes);
if (!pipes)
dm_allow_self_refresh_and_mclk_switch;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states) {
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) {
if (allow_self_refresh_only) {
/*
context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
dm_allow_self_refresh;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
} else {
goto validate_fail;
struct dc *dc,
struct dcn21_resource_pool *pool)
{
- int i, j;
+ unsigned int i;
+ int j;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
DC_FP_START();
enum mmhubbub_wbif_mode wbif_mode;
struct display_mode_lib *dml = &context->bw_ctx.dml;
struct mcif_arb_params *wb_arb_params;
- int i, j, dwb_pipe;
+ int j, dwb_pipe;
+ unsigned int i;
/* Writeback MCIF_WB arbitration parameters */
dwb_pipe = 0;
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
bool newly_split[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel = 0;
+ unsigned int i;
+ int pipe_cnt, pipe_idx, vlevel = 0;
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
ASSERT(pipes);
dm_allow_self_refresh_and_mclk_switch;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (vlevel < context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states)
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
}
if (allow_self_refresh_only &&
dm_allow_self_refresh;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) {
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
if (bw_params->clk_table.entries[0].memclk_mhz) {
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
- if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
+ if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz)
dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
- if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
+ if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz)
dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
- if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
+ if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz)
dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
- if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
+ if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz)
dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
}
dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
DC_FP_END();
- if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
num_dcfclk_sta_targets++;
- } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ } else if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
for (i = 0; i < num_dcfclk_sta_targets; i++) {
- if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
+ if (dcfclk_sta_targets[i] > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
break;
}
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
- if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
+ if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
}
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
- optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
+ optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
struct dc *dc,
struct dcn30_resource_pool *pool)
{
- int i;
+ unsigned int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
struct ddc_service_init_data ddc_init_data = {0};
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
pool->base.opps[i] = dcn30_opp_create(ctx, i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.timing_generators[i] = dcn30_timing_generator_create(
ctx, i);
if (pool->base.timing_generators[i] == NULL) {
}
/* ABM */
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.multiple_abms[i] = dmub_abm_create(ctx,
&abm_regs[i],
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[i] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
struct dc *dc,
struct dcn301_resource_pool *pool)
{
- int i, j;
+ int j;
+ unsigned int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
/* ABM (or ABMs for NV2x) */
/* TODO: */
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.multiple_abms[i] = dmub_abm_create(ctx,
&abm_regs[i],
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[i] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
}
}
- for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) {
if (pool->dscs[i] != NULL)
dcn20_dsc_destroy(&pool->dscs[i]);
}
dal_irq_service_destroy(&pool->irqs);
}
- for (i = 0; i < pool->res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) {
if (pool->engines[i] != NULL)
dce110_engine_destroy(&pool->engines[i]);
if (pool->hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) {
if (pool->opps[i] != NULL)
pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
}
- for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) {
if (pool->timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
pool->timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) {
if (pool->dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
pool->dwbc[i] = NULL;
if (pool->dp_clock_source != NULL)
dcn20_clock_source_destroy(&pool->dp_clock_source);
- for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) {
if (pool->mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->mpc_lut[i]);
pool->mpc_lut[i] = NULL;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->clk_src_count; i++) {
+ for (i = 0; i < (int)pool->clk_src_count; i++) {
if (pool->clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->pipe_count; i++) {
+ for (i = 0; i < (int)pool->pipe_count; i++) {
pool->hubps[i] = dcn302_hubp_create(ctx, i);
if (pool->hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
}
}
- for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) {
if (pool->dscs[i] != NULL)
dcn20_dsc_destroy(&pool->dscs[i]);
}
dal_irq_service_destroy(&pool->irqs);
}
- for (i = 0; i < pool->res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) {
if (pool->engines[i] != NULL)
dce110_engine_destroy(&pool->engines[i]);
if (pool->hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) {
if (pool->opps[i] != NULL)
pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
}
- for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) {
if (pool->timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
pool->timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) {
if (pool->dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
pool->dwbc[i] = NULL;
if (pool->dp_clock_source != NULL)
dcn20_clock_source_destroy(&pool->dp_clock_source);
- for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) {
if (pool->mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->mpc_lut[i]);
pool->mpc_lut[i] = NULL;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->clk_src_count; i++) {
+ for (i = 0; i < (int)pool->clk_src_count; i++) {
if (pool->clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->pipe_count; i++) {
+ for (i = 0; i < (int)pool->pipe_count; i++) {
pool->hubps[i] = dcn303_hubp_create(ctx, i);
if (pool->hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
enum dc_validate_mode validate_mode)
{
uint32_t pipe_cnt;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i, pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
/* Only apply for dual stream scenarios with edp*/
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt, crb_idx, crb_pipes;
+ unsigned int i;
+ int pipe_cnt, crb_idx, crb_pipes;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {
bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
- split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
+ split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
/* Minimum 2 segments to allow mpc/odm combine if its used later */
continue;
}
- bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
+ bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0)
(max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
} else if (!is_dual_plane(pipe->plane_state->format)
&& pipe->plane_state->src_rect.width <= 5120
- && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
+ && (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
/* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
pipes[0].pipe.src.unbounded_req_mode = true;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
bool subvp_in_use = false;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc_obj(struct dcn20_link_encoder);
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn401_dsc_destroy(&pool->base.dscs[i]);
}
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else if (dc_is_dp_signal(stream->signal)) {
/* round up to nearest power of 2, or max at 8 pixels per cycle */
- if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 8;
- } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 4;
- } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
int dcn401_get_power_profile(const struct dc_state *context)
{
- int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
+ unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
int dpm_level = 0;
- for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
+ for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
break;
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn42_dsc_destroy(&pool->base.dscs[i]);
}
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else if (dc_is_dp_signal(stream->signal)) {
/* round up to nearest power of 2, or max at 8 pixels per cycle */
- if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 8;
- } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 4;
- } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
struct dc *dc,
struct dcn42_resource_pool *pool)
{
- int i, j;
+ unsigned int i, j;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses;
num_pipes = pool->base.res_cap->num_dpp;
pipe_fuses = read_pipe_fuses(ctx);
- for (i = 0; i < pool->base.res_cap->num_dpp; i++)
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dpp; i++)
if (pipe_fuses & 1 << i)
num_pipes--;
}
/* HUBPs, DPPs, OPPs, TGs, ABMs */
- for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0, j = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
/* if pipe is disabled, skip instance of HW pipe,
* i.e, skip ASIC register instance
*/
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[j] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
}
/* DSCs */
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn42_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn42_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
projects / thirdparty / kernel / linux.git / commitdiff
