drm/amdgpu/gfx7: align mqd settings with KFD

Make sure to set the quantum bits in the compute MQD
for better fairness across queues of the same priority.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2b691452775bc41f339aa67ed80b97e6acc3aea1..65b8497ad5f023b08632b91bec229a35673e11cb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2819,6 +2819,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
 {
        u64 hqd_gpu_addr;
        u64 wb_gpu_addr;
+       u32 tmp;
 
        /* init the mqd struct */
        memset(mqd, 0, sizeof(struct cik_mqd));
@@ -2923,7 +2924,11 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
        mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
        mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
        mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
-       mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+       tmp = RREG32(mmCP_HQD_QUANTUM);
+       tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+       tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+       tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);
+       mqd->cp_hqd_quantum = tmp;
        mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
        mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
        mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);