drm/amdgpu/gfx9.4.3: skip PTL disable during GPU reset

During RAS UE-triggered GPU reset, gfx_v9_4_3_hw_fini() attempts to
send a PTL disable command to PSP. Since PSP is unresponsive at that
point, this produces spurious error logs on all hive nodes:
  PTL command 0xa0000001 failed, PSP response status: 0xFFFFFFFF
  PTL initialization failed (-5)
Skip the PTL disable command when GPU reset is in progress, as PTL
will be properly re-initialized during post-reset recovery via
gfx_v9_4_3_late_init().

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index d0e7212519f9bf229b75969e0f8e14951d19fffe..f895c3ef56bc00a8b4e6c608becd1c06534bbeb8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2443,7 +2443,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block)
        struct amdgpu_device *adev = ip_block->adev;
        int i, num_xcc;
 
-       if (adev->psp.ptl.hw_supported)
+       if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev))
                gfx_v9_4_3_perf_monitor_ptl_init(adev, false);
 
        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);