drm: renesas: rzg2l_mipi_dsi: Move rzg2l_mipi_dsi_set_display_timing()

The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1,
requires display timings to be set after the HS clock is started. Move
rzg2l_mipi_dsi_set_display_timing() from
rzg2l_mipi_dsi_atomic_pre_enable() to rzg2l_mipi_dsi_atomic_enable(),
placing it after rzg2l_mipi_dsi_start_hs_clock(). Drop the unused ret
variable from rzg2l_mipi_dsi_atomic_pre_enable().

Fixes: 5ce16c169a4c ("drm: renesas: rz-du: Add atomic_pre_enable")
Fixes: 7a043f978ed1 ("drm: rcar-du: Add RZ/G2L DSI driver")
Cc: stable@vger.kernel.org
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20260330104450.128512-2-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index a87a301326c7aa4396dfb8551a226960b62417d9..ff95cb9a7de5fac32b553c9ad3d96a9b8a27a688 100644 (file)
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -1025,29 +1025,33 @@ static void rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge *bridge,
        const struct drm_display_mode *mode;
        struct drm_connector *connector;
        struct drm_crtc *crtc;
-       int ret;
 
        connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
        crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
        mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
 
-       ret = rzg2l_mipi_dsi_startup(dsi, mode);
-       if (ret < 0)
-               return;
-
-       rzg2l_mipi_dsi_set_display_timing(dsi, mode);
+       rzg2l_mipi_dsi_startup(dsi, mode);
 }
 
 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
                                         struct drm_atomic_state *state)
 {
        struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
+       const struct drm_display_mode *mode;
+       struct drm_connector *connector;
+       struct drm_crtc *crtc;
        int ret;
 
        ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
        if (ret < 0)
                goto err_stop;
 
+       connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+       crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
+       mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
+
+       rzg2l_mipi_dsi_set_display_timing(dsi, mode);
+
        ret = rzg2l_mipi_dsi_start_video(dsi);
        if (ret < 0)
                goto err_stop_clock;