void init_wdog(void)
{
- disable_wdog((void __iomem *)WDG3_RBASE);
+ ofnode node;
+
+ ofnode_for_each_compatible_node(node, "fsl,imx8ulp-wdt") {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
+ }
}
static struct mm_region imx8ulp_arm64_mem_map[] = {
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
- if (!IS_ENABLED(CONFIG_IMX952)) {
- disable_wdog((void __iomem *)WDG3_BASE_ADDR);
- disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ ofnode node;
+
+ ofnode_for_each_compatible_node(node, "fsl,imx93-wdt") {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
}
gpio_reset(GPIO2_BASE_ADDR);
void init_wdog(void)
{
- disable_wdog((void __iomem *)WDG3_BASE_ADDR);
- disable_wdog((void __iomem *)WDG4_BASE_ADDR);
- disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+ ofnode node;
+
+ ofnode_for_each_compatible_node(node, "fsl,imx93-wdt") {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((void __iomem *)base);
+ }
}
static struct mm_region imx93_mem_map[] = {
return LOW_POWER_BOOT;
}
+static void init_wdog(void);
int arch_cpu_init(void)
{
+ /* Disable wdog */
+ init_wdog();
+
enable_ca7_smp();
return 0;
}
while (!(readl(wdog_base + 0x00) & 0x400));
}
-void init_wdog(void)
+static void init_wdog(void)
{
/*
* ROM will configure WDOG1, disable it or enable it
* In this function, we will disable both WDOG1 and WDOG2,
* and set update bit for both. So that kernel can reconfigure them.
*/
- disable_wdog(WDG1_RBASE);
- disable_wdog(WDG2_RBASE);
+ ofnode node;
+
+ ofnode_for_each_compatible_node(node, "fsl,imx7ulp-wdt") {
+ phys_addr_t base;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ continue;
+
+ disable_wdog((u32)base);
+ }
}
static bool ldo_mode_is_enabled(void)
void s_init(void)
{
- /* Disable wdog */
- init_wdog();
-
/* clock configuration. */
clock_init();