drm/ast: Add constant for VGACR91

Register VGACR91 receives a password that enables the new mode-info
header in other registers. Replace the password's magic value with a
constant.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260414070522.33943-2-tzimmermann@suse.de

diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 21abb6a6d8bcdc23870f9d5d72a0a5ee410a4af9..c150b83aaca797ee02f59b8befb0c96ef1fb2676 100644 (file)
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -168,7 +168,7 @@ static void ast_set_vbios_color_reg(struct ast_device *ast,
        ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
 
        if (vmode->flags & NewModeInfo) {
-               ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8);
+               ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD);
                ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8);
        }
 }
@@ -188,7 +188,7 @@ static void ast_set_vbios_mode_reg(struct ast_device *ast,
        ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
 
        if (vmode->flags & NewModeInfo) {
-               ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8);
+               ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, AST_IO_VGACR91_PASSWORD);
                ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000);
                ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay);
                ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8);

diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index ea7dc382aee7116a59bbd112ce7bbfef6556e37d..99d0a8322f897c44da0f32984b32da7fe4bfbfa9 100644 (file)
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -31,6 +31,7 @@
 #define AST_IO_VGACRI                  (0x54)
 #define AST_IO_VGACR17_SYNC_ENABLE     BIT(7) /* called "Hardware reset" in docs */
 #define AST_IO_VGACR80_PASSWORD                (0xa8)
+#define AST_IO_VGACR91_PASSWORD                (0xa8)
 #define AST_IO_VGACR99_VGAMEM_RSRV_MASK        GENMASK(1, 0)
 #define AST_IO_VGACRA1_VGAIO_DISABLED  BIT(1)
 #define AST_IO_VGACRA1_MMIO_ENABLED    BIT(2)