arm64: dts: renesas: r9a08g046: Add OPP table

Add OPP table for RZ/G3L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430125342.439755-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 236a675231e56641d6557bc02c959ae74b4b48bd..e52498b3a745edfd83b47559f37ff9a35ae0c5a0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -14,6 +14,42 @@
        #size-cells = <2>;
        interrupt-parent = <&gic>;
 
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+
+               opp-37500000 {
+                       opp-hz = /bits/ 64 <37500000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-75000000 {
+                       opp-hz = /bits/ 64 <75000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-150000000 {
+                       opp-hz = /bits/ 64 <150000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <300000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -24,6 +60,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu1: cpu@100 {
@@ -32,6 +70,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu2: cpu@200 {
@@ -40,6 +80,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu3: cpu@300 {
@@ -48,6 +90,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                L3_CA55: cache-controller-0 {