arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base

The board exposes the GPIO4_B5 pin to control the voltage bias on the
HDMI0 data lines.  It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.

Wire up the hdmi0 node to its dedicated GPIO via frl-enable-gpios to
allow adjusting the bias when transitioning between TMDS and FRL modes.

While at it, rename the hdmi_frl_pin pinmux to hdmi0_tx_on_h, in line
with the naming commonly used in RK3588s-bassed board schematics.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260428-dts-rk-frl-enable-gpios-v2-8-924df9db884a@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
index 06120b2db690a95b69ae49dbbc4c78aae96012ee..20da0c2b3d92ea0924b5ce45642ff24d0d4dc334 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
@@ -143,10 +143,11 @@
 };
 
 &hdmi0 {
-       pinctrl-names = "default";
+       frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
        pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
                     &hdmim0_tx0_scl &hdmim0_tx0_sda
-                    &hdmi_frl_pin>;
+                    &hdmi0_tx_on_h>;
+       pinctrl-names = "default";
        status = "okay";
 };
 
@@ -245,8 +246,8 @@
        };
 
        hdmi {
-               hdmi_frl_pin: hdmi-frl-pin {
-                       rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+               hdmi0_tx_on_h: hdmi0-tx-on-h {
+                       rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
        };