struct fixed31_32;
struct tetrahedral_params;
-#ifdef CONFIG_DRM_AMD_DC_KUNIT_TEST
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
/*
* Prototypes for functions exposed to KUnit tests. The enum types
* used below (dc_transfer_func_predefined, amdgpu_transfer_function,
#include "amdgpu.h"
#include "amdgpu_dm_colorop.h"
+#include "amdgpu_dm_kunit_helpers.h"
#include "dc.h"
const u64 amdgpu_dm_supported_degam_tfs =
BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
+EXPORT_IF_KUNIT(amdgpu_dm_supported_degam_tfs);
const u64 amdgpu_dm_supported_shaper_tfs =
BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |
BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |
BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |
BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
+EXPORT_IF_KUNIT(amdgpu_dm_supported_shaper_tfs);
const u64 amdgpu_dm_supported_blnd_tfs =
BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
+EXPORT_IF_KUNIT(amdgpu_dm_supported_blnd_tfs);
#define MAX_COLOR_PIPELINE_OPS 10
#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
+#include "dc_types.h"
+
struct drm_crtc;
struct dm_crtc_state;
+struct amdgpu_device;
enum amdgpu_dm_pipe_crc_source {
AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
#define amdgpu_dm_crtc_secure_display_create_contexts(x)
#endif
-#ifdef CONFIG_DRM_AMD_DC_KUNIT_TEST
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source);
bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src);
bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src);
struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc);
-#ifdef CONFIG_DRM_AMD_DC_KUNIT_TEST
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
void process_output(struct hdcp_workqueue *hdcp_work);
#endif
struct dc_stream_state *stream, bool set_event, enum psr_event event,
bool wait_for_disable);
-#ifdef CONFIG_DRM_AMD_DC_KUNIT_TEST
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
void amdgpu_dm_psr_fill_caps(struct dc_link *link, struct psr_caps *caps);
#endif
BIT(DRM_COLOROP_1D_CURVE_GAMMA22));
}
-static void dm_test_supported_degam_tfs_no_extra_bits(struct kunit *test)
+static void dm_test_supported_shaper_tfs_no_extra_bits(struct kunit *test)
{
- u64 expected = BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
- BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
- BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
- BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
+ u64 expected = BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |
+ BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |
+ BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |
+ BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
KUNIT_EXPECT_EQ(test, amdgpu_dm_supported_shaper_tfs, expected);
}