arm64: dts: qcom: Add support for MM clock controllers for Glymur

Add the device nodes for the multimedia clock controllers videocc, gpucc
and gxclkctl.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 8a239dc359b0f5623c23a9f8a89a61619465921b..5e7c5320dc20baee2f6170761bc754ab976bb371 100644 (file)
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -5,7 +5,10 @@
 
 #include <dt-bindings/clock/qcom,glymur-dispcc.h>
 #include <dt-bindings/clock/qcom,glymur-gcc.h>
+#include <dt-bindings/clock/qcom,glymur-gpucc.h>
 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
+#include <dt-bindings/clock/qcom,glymur-videocc.h>
+#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -3742,6 +3745,34 @@
                        #interconnect-cells = <2>;
                };
 
+               gxclkctl: clock-controller@3d64000 {
+                       compatible = "qcom,glymur-gxclkctl";
+                       reg = <0x0 0x03d64000 0x0 0x6000>;
+
+                       power-domains = <&rpmhpd RPMHPD_GFX>,
+                                       <&rpmhpd RPMHPD_GMXC>,
+                                       <&gpucc GPU_CC_CX_GDSC>;
+
+                       #power-domain-cells = <1>;
+               };
+
+               gpucc: clock-controller@3d90000 {
+                       compatible = "qcom,glymur-gpucc";
+                       reg = <0x0 0x03d90000 0x0 0x9800>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+                               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+                       power-domains = <&rpmhpd RPMHPD_MX>,
+                                       <&rpmhpd RPMHPD_CX>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                ipcc: mailbox@3e04000 {
                        compatible = "qcom,glymur-ipcc", "qcom,ipcc";
                        reg = <0x0 0x03e04000 0x0 0x1000>;
@@ -4637,6 +4668,22 @@
                        };
                };
 
+               videocc: clock-controller@aaf0000 {
+                       compatible = "qcom,glymur-videocc";
+                       reg = <0x0 0x0aaf0000 0x0 0x10000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>;
+
+                       power-domains = <&rpmhpd RPMHPD_MMCX>,
+                                       <&rpmhpd RPMHPD_MXC>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                dispcc: clock-controller@af00000 {
                        compatible = "qcom,glymur-dispcc";
                        reg = <0x0 0x0af00000 0x0 0x20000>;