drm/amd/amdgpu : Distribute inv_tlbs on individual XCC

From MES version 0x74 and above, pipe 1(kiq) support use the
shared command buffer to distribute the tasks among the xccs
within the same partition. It's more efficient for tlb invalidation
been done individually on the each XCC at the same time compare
to let master xcc loop all xccs.

This requires the coop_mode been set before kiq set_hw_resource.

Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
index 456dbbcfce1e88bf860c0e20ee6ae6a25f6490da..3023cf6ab1ba5bea5ba6b955534abfa23f92b5ee 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
@@ -44,6 +44,7 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block);
 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id);
+static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id);
 
 #define MES_EOP_SIZE   2048
 
@@ -621,11 +622,15 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
        mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
        mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
 
-       if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) {
+       /* From version 0x74 above, pipe1 support use shared command buffer
+          to distribute some tasks on individual XCCs*/
+       if (mes->enable_coop_mode &&
+           ((pipe == AMDGPU_MES_SCHED_PIPE) ||
+           ((mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) {
                master_xcc_id = mes->master_xcc_ids[inst];
                mes_set_hw_res_1_pkt.mes_coop_mode = 1;
                mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr =
-                       mes->shared_cmd_buf_gpu_addr[master_xcc_id];
+                       mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe];
        }
 
        return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
@@ -1148,9 +1153,6 @@ static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev,
 {
        int r, inst = MES_PIPE_INST(xcc_id, pipe);
 
-       if (pipe == AMDGPU_MES_KIQ_PIPE)
-               return 0;
-
        r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
                                    AMDGPU_GEM_DOMAIN_VRAM,
                                    &adev->mes.shared_cmd_buf_obj[inst],
@@ -1714,6 +1716,10 @@ static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id)
                goto failure;
 
        if (adev->enable_uni_mes) {
+               r = mes_v12_1_setup_coop_mode(adev, xcc_id);
+               if (r)
+                       goto failure;
+
                r = mes_v12_1_set_hw_resources(&adev->mes,
                                                 AMDGPU_MES_KIQ_PIPE, xcc_id);
                if (r)
@@ -1836,9 +1842,6 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id)
                goto failure;
 
        if (adev->enable_uni_mes) {
-               r = mes_v12_1_setup_coop_mode(adev, xcc_id);
-               if (r)
-                       goto failure;
                mes_v12_1_set_hw_resources_1(&adev->mes,
                                               AMDGPU_MES_SCHED_PIPE, xcc_id);
        }