realtek: rtl9303: split Hasivo S1100W(P)-8XGT-SE

Hasivo has two RJ45-only 8-port 10G switches, S1100W-8XGT-SE (non-PoE)
and S1100WP-8XGT-SE (PoE). The boards are both identical, with the
exception that the S1100WP-8XGT-SE has 2x HS104 PoE chips.

Make a shared dtsi to share between both variants.

Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24349
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>

diff --git a/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se-common.dtsi b/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se-common.dtsi
new file mode 100644 (file)
index 0000000..c3107a6
--- /dev/null
+++ b/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se-common.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
+                     <0x20000000 0x10000000>; /* 256 MiB highmem */
+       };
+
+       aliases {
+               led-boot = &led_sys;
+               led-failsafe = &led_sys;
+               led-running = &led_sys;
+               led-upgrade = &led_sys;
+       };
+
+       chosen {
+               stdout-path = "serial0:38400n8";
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               button-reset {
+                       label = "reset";
+                       gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_RESTART>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               led_sys: led-0 {
+                       gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_STATUS;
+               };
+       };
+
+       led_set {
+               compatible = "realtek,rtl9300-leds";
+               active-low;
+
+               /*
+                * LED set 0
+                *
+                * - LED[0](Amber): 5G/LINK/ACT
+                * - LED[1](Green): 10G/LINK/ACT
+                * - LED[2](Amber): 1G/100M/10M/LINK/ACT
+                * - LED[3](Green): 2.5G/LINK/ACT
+                */
+               led_set0 = <(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+                           (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+                           (RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
+                            RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+                           (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
+       };
+};
+
+&spi0 {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       /* stock is LOADER */
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0x0000000 0x00e0000>;
+                               read-only;
+                       };
+
+                       /* stock is BDINFO */
+                       partition@e0000 {
+                               label = "u-boot-env";
+                               reg = <0x00e0000 0x0010000>;
+                       };
+
+                       /* stock is SYSINFO */
+                       partition@f0000 {
+                               label = "u-boot-env2";
+                               reg = <0x00f0000 0x0010000>;
+                               read-only;
+                       };
+
+                       /* stock is JFFS2_CFG */
+                       partition@100000 {
+                               label = "jffs";
+                               reg = <0x0100000 0x0100000>;
+                       };
+
+                       /* stock is JFFS2_LOG */
+                       partition@200000 {
+                               label = "jffs2";
+                               reg = <0x0200000 0x0100000>;
+                       };
+
+                       /* stock is RUNTIME */
+                       partition@300000 {
+                               compatible = "openwrt,uimage", "denx,uimage";
+                               label = "firmware";
+                               reg = <0x0300000 0x0c00000>;
+                       };
+
+                       /* stock is OEMINFO */
+                       partition@f00000 {
+                               label = "oeminfo";
+                               reg = <0x0f00000 0x0100000>;
+                               read-only;
+                       };
+               };
+       };
+};
+
+&switch0 {
+       ethernet-ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
+               SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
+               SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
+               SWITCH_PORT_LED(20, 4, 5, 0, 0, usxgmii)
+               SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
+               SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
+               SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
+               SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
+
+               /* Internal SoC */
+               port@28 {
+                       ethernet = <&ethernet0>;
+                       reg = <28>;
+                       phy-mode = "internal";
+
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};
+
+&mdio_bus0 {
+       ethernet-phy-package@0 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;
+
+               PHY_C45(0, 0)
+               PHY_C45(8, 1)
+               PHY_C45(16, 2)
+               PHY_C45(20, 3)
+       };
+};
+
+&mdio_bus3 {
+       ethernet-phy-package@16 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <16>;
+
+               PHY_C45(24, 16)
+               PHY_C45(25, 17)
+               PHY_C45(26, 18)
+               PHY_C45(27, 19)
+       };
+};
+
+&phy0 { tx-polarity = <PHY_POL_INVERT>; };
+&phy8 { rx-polarity = <PHY_POL_INVERT>; };
+&phy16 { tx-polarity = <PHY_POL_INVERT>; };
+&phy20 { rx-polarity = <PHY_POL_INVERT>; };
+&phy24 { tx-polarity = <PHY_POL_INVERT>; };
+&phy25 { rx-polarity = <PHY_POL_INVERT>; };
+&phy26 { tx-polarity = <PHY_POL_INVERT>; };
+&phy27 { rx-polarity = <PHY_POL_INVERT>; };

diff --git a/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts b/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
index d079d681492101f996e9e3f91b8fe4d5fc4789d5..5483e262a1f35a448be43b87101311996134a6f0 100644 (file)
--- a/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
+++ b/target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
@@ -1,183 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include "rtl930x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
+#include "rtl9303_hasivo_s1100w-8xgt-se-common.dtsi"
 
 / {
        compatible = "hasivo,s1100w-8xgt-se", "realtek,rtl930x-soc";
        model = "Hasivo S1100W-8XGT-SE";
-
-       memory@0 {
-               device_type = "memory";
-               reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
-                     <0x20000000 0x10000000>; /* 256 MiB highmem */
-       };
-
-       aliases {
-               led-boot = &led_sys;
-               led-failsafe = &led_sys;
-               led-running = &led_sys;
-               led-upgrade = &led_sys;
-       };
-
-       chosen {
-               stdout-path = "serial0:38400n8";
-       };
-
-       keys {
-               compatible = "gpio-keys";
-
-               button-reset {
-                       label = "reset";
-                       gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
-                       linux,code = <KEY_RESTART>;
-               };
-       };
-
-       leds {
-               compatible = "gpio-leds";
-
-               led_sys: led-0 {
-                       gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
-                       color = <LED_COLOR_ID_GREEN>;
-                       function = LED_FUNCTION_STATUS;
-               };
-       };
-
-       led_set {
-               compatible = "realtek,rtl9300-leds";
-               active-low;
-
-               /*
-                * LED set 0
-                *
-                * - LED[0](Amber): 5G/LINK/ACT
-                * - LED[1](Green): 10G/LINK/ACT
-                * - LED[2](Amber): 1G/100M/10M/LINK/ACT
-                * - LED[3](Green): 2.5G/LINK/ACT
-                */
-               led_set0 = <(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
-                           (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
-                           (RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
-                            RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
-                           (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
-       };
 };
-
-&spi0 {
-       status = "okay";
-
-       flash@0 {
-               compatible = "jedec,spi-nor";
-               reg = <0>;
-               spi-max-frequency = <10000000>;
-
-               partitions {
-                       compatible = "fixed-partitions";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-
-                       /* stock is LOADER */
-                       partition@0 {
-                               label = "u-boot";
-                               reg = <0x0000000 0x00e0000>;
-                               read-only;
-                       };
-
-                       /* stock is BDINFO */
-                       partition@e0000 {
-                               label = "u-boot-env";
-                               reg = <0x00e0000 0x0010000>;
-                       };
-
-                       /* stock is SYSINFO */
-                       partition@f0000 {
-                               label = "u-boot-env2";
-                               reg = <0x00f0000 0x0010000>;
-                               read-only;
-                       };
-
-                       /* stock is JFFS2_CFG */
-                       partition@100000 {
-                               label = "jffs";
-                               reg = <0x0100000 0x0100000>;
-                       };
-
-                       /* stock is JFFS2_LOG */
-                       partition@200000 {
-                               label = "jffs2";
-                               reg = <0x0200000 0x0100000>;
-                       };
-
-                       /* stock is RUNTIME */
-                       partition@300000 {
-                               compatible = "openwrt,uimage", "denx,uimage";
-                               label = "firmware";
-                               reg = <0x0300000 0x0c00000>;
-                       };
-
-                       /* stock is OEMINFO */
-                       partition@f00000 {
-                               label = "oeminfo";
-                               reg = <0x0f00000 0x0100000>;
-                               read-only;
-                       };
-               };
-       };
-};
-
-&mdio_bus0 {
-       PHY_C45(0, 0)
-       PHY_C45(8, 1)
-       PHY_C45(16, 2)
-       PHY_C45(20, 3)
-};
-
-&mdio_bus3 {
-       PHY_C45(24, 16)
-       PHY_C45(25, 17)
-       PHY_C45(26, 18)
-       PHY_C45(27, 19)
-};
-
-&switch0 {
-       ethernet-ports {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
-               SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
-               SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
-               SWITCH_PORT_LED(20, 4, 5, 0, 0, usxgmii)
-               SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
-               SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
-               SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
-               SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
-
-               /* Internal SoC */
-               port@28 {
-                       ethernet = <&ethernet0>;
-                       reg = <28>;
-                       phy-mode = "internal";
-
-                       fixed-link {
-                               speed = <1000>;
-                               full-duplex;
-                       };
-               };
-       };
-};
-
-&phy0 { tx-polarity = <PHY_POL_INVERT>; };
-&phy8 { rx-polarity = <PHY_POL_INVERT>; };
-&phy16 { tx-polarity = <PHY_POL_INVERT>; };
-&phy20 { rx-polarity = <PHY_POL_INVERT>; };
-&phy24 { tx-polarity = <PHY_POL_INVERT>; };
-&phy25 { rx-polarity = <PHY_POL_INVERT>; };
-&phy26 { tx-polarity = <PHY_POL_INVERT>; };
-&phy27 { rx-polarity = <PHY_POL_INVERT>; };