clk: renesas: rzg2l: Drop always-false check in rzg3s_cpg_pll_clk_recalc_rate()

Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the
function is SoC-specific.

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326110648.29389-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index abfd8634d2bef214e309ba97000dbd9eed438070..910c16a369a5385658d764d13bd84bb2a2344bf9 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1107,9 +1107,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
        u32 nir, nfr, mr, pr, val, setting;
        u64 rate;
 
-       if (pll_clk->type != CLK_TYPE_G3S_PLL)
-               return parent_rate;
-
        setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
        if (setting) {
                val = readl(priv->base + setting);