clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks

Add the CLK_PLLDSI0_CSDIV and CLK_PLLDSI1_CSDIV fixed-factor clocks to
the r9a09g047 SoC clock driver.

These clocks are required to enable DSI and RGB output support.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/4d5b4ddad89770447b3818381d5353f5065b72b5.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index fd9b49c39dac8f93a06ad6eeb0f898f8effb9e8d..82aae32d50e129a7baa73ca090de720ef0bdf04d 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -71,6 +71,8 @@ enum clk_ids {
        CLK_PLLETH_LPCLK,
        CLK_PLLDSI0_DIV7,
        CLK_PLLDSI1_DIV7,
+       CLK_PLLDSI0_CSDIV,
+       CLK_PLLDSI1_CSDIV,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -98,6 +100,18 @@ static const struct clk_div_table dtable_2_16[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_16_plldsi[] = {
+       {0, 2},
+       {1, 4},
+       {2, 6},
+       {3, 8},
+       {4, 10},
+       {5, 12},
+       {6, 14},
+       {7, 16},
+       {0, 0},
+};
+
 static const struct clk_div_table dtable_2_64[] = {
        {0, 2},
        {1, 4},
@@ -198,6 +212,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
                  CSDIV0_DIVCTL2, dtable_16_128),
 
+       DEF_PLLDSI_DIV(".plldsi0_csdiv", CLK_PLLDSI0_CSDIV, CLK_PLLDSI0,
+                      CSDIV1_DIVCTL2, dtable_2_16_plldsi),
+       DEF_PLLDSI_DIV(".plldsi1_csdiv", CLK_PLLDSI1_CSDIV, CLK_PLLDSI1,
+                      CSDIV1_DIVCTL3, dtable_2_16_plldsi),
        DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
        DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
 

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 74a3824d605e3b866dae8938d541e344cf57d134..33bc3c27291c8932e68f18d8f6dfcdafdc3bd9f9 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -148,6 +148,7 @@ struct fixed_mod_conf {
 #define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
 #define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
+#define CSDIV1_DIVCTL3 DDIV_PACK(CPG_CSDIV1, 12, 4, CSDIV_NO_MON)
 
 #define SSEL0_SELCTL2  SMUX_PACK(CPG_SSEL0, 8, 1)
 #define SSEL0_SELCTL3  SMUX_PACK(CPG_SSEL0, 12, 1)