pmdomain: mediatek: Fix mt8183 hang on boot

Depending on firmware, part of the MFG domains may be partially left ON
at boot time with kernel detecting PD as ON, while it's OFF.

Some of MFG cores may be left powered after bootloader, to let the ACP to
prefetch the GPU region when the display controller is brought up for a
continuous splash animation performed by downstream stack.

This doesn't play well with an eventual delay in probing upstream Panfrost
driver when the display controller is fully set up, as that would make
genpd's sync_state() to power off the domain while ACP tries to prefetch:
this is causing an AXI stall, effectively freezing the AP indefinitely.

In order to prevent trouble from happening, the sync_state() functionality
must be obliterated on all of the MFG domains: while this guarantees a
power leakage if the bootloader boots the kernel with MFG PDs partially
powered on, this is the only way to ensure stable operation of the SoC
during boot on devices with such firmware because, of course, those will
never officially receive a firmware update.

Fixes Kappa Chromebook hanging during system boot.

Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state")
Fixes: 13a4b7fb6260 ("pmdomain: core: Leave powered-on genpds on until late_initcall_sync")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulfh@kernel.org>

diff --git a/drivers/pmdomain/mediatek/mt8183-pm-domains.h b/drivers/pmdomain/mediatek/mt8183-pm-domains.h
index 3742782a2702e49a36caac1b461ef2fe0de32246..5e33b8628e8527dc3c3e68caff6f27fbf432c9fc 100644 (file)
--- a/drivers/pmdomain/mediatek/mt8183-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8183-pm-domains.h
@@ -47,7 +47,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = 0,
                .sram_pdn_ack_bits = 0,
-               .caps = MTK_SCPD_DOMAIN_SUPPLY,
+               .caps = MTK_SCPD_DOMAIN_SUPPLY | MTK_SCPD_KEEP_DEFAULT_OFF,
        },
        [MT8183_POWER_DOMAIN_MFG] = {
                .name = "mfg",
@@ -57,7 +57,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
-               .caps = MTK_SCPD_DOMAIN_SUPPLY,
+               .caps = MTK_SCPD_DOMAIN_SUPPLY | MTK_SCPD_KEEP_DEFAULT_OFF,
        },
        [MT8183_POWER_DOMAIN_MFG_CORE0] = {
                .name = "mfg_core0",
@@ -67,6 +67,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
+               .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
        },
        [MT8183_POWER_DOMAIN_MFG_CORE1] = {
                .name = "mfg_core1",
@@ -76,6 +77,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
+               .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
        },
        [MT8183_POWER_DOMAIN_MFG_2D] = {
                .name = "mfg_2d",
@@ -85,6 +87,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
+               .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
                .bp_cfg = {
                        BUS_PROT_WR(INFRA,
                                    MT8183_TOP_AXI_PROT_EN_1_MFG,