clk: mediatek: add MUX_CLR_SET macro

Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
a clock gate nor an update register.

Add a MUX_CLR_SET convenience macro that takes only the mux register
offsets, bit shift, and width, hardcoding upd_ofs = 0 and
upd_shift = -1 so callers cannot accidentally pass bogus sentinel
values to wrongly-typed fields.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
index 151e56dcf88427c33301371afa2885b119e9641f..1a9baf306b4a752010bf112dcad799ae8403670d 100644 (file)
--- a/drivers/clk/mediatek/clk-mux.h
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -126,6 +126,11 @@ extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
                        0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,         \
                        mtk_mux_clr_set_upd_ops)
 
+#define MUX_CLR_SET(_id, _name, _parents, _mux_ofs,                    \
+                   _mux_set_ofs, _mux_clr_ofs, _shift, _width)         \
+                   MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,     \
+                   _mux_set_ofs, _mux_clr_ofs, _shift, _width, 0, -1)
+
 #define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents,                      \
                                _mux_ofs, _mux_set_ofs, _mux_clr_ofs,                   \
                                _hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs,               \