INTEL_PLANE_CAP_NEED64K_PHYS);
}
+bool intel_fb_needs_cpu_access(const struct drm_framebuffer *fb)
+{
+ return intel_fb_rc_ccs_cc_plane(fb) >= 0;
+}
+
/**
* intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type
* @modifier: Modifier to check
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_needs_64k_phys(u64 modifier);
bool intel_fb_is_tile4_modifier(u64 modifier);
+bool intel_fb_needs_cpu_access(const struct drm_framebuffer *fb);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
* ensure it is always in the mappable part of lmem, if this is
* a small-bar device.
*/
- if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
+ if (intel_fb_needs_cpu_access(fb))
flags &= ~I915_BO_ALLOC_GPU_ONLY;
ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
flags);
refcount_set(&vma->ref, 1);
if (IS_DGFX(to_xe_device(bo->ttm.base.dev)) &&
- intel_fb_rc_ccs_cc_plane(&fb->base) >= 0 &&
+ intel_fb_needs_cpu_access(&fb->base) &&
!(bo->flags & XE_BO_FLAG_NEEDS_CPU_ACCESS)) {
struct xe_vram_region *vram = xe_device_get_root_tile(xe)->mem.vram;