clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK

Add support for the SMUX2_DSI0_CLK and SMUX2_DSI1_CLK clock muxes
present on the r9a09g047 SoC.

These muxes select between CDIV7_DSI{0,1}_CLK and CSDIV_2to16_PLLDSI{0,1}
using the CPG_SSEL3 register (SELCTL0 and SELCTL1 bits).

According to the hardware manual, when LVDS0 or LVDS1 outputs are used,
SELCTL0 or SELCTL1 must be set accordingly.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9595f56ce8ab120477bfc11eaafb0f2b655d049a.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 82aae32d50e129a7baa73ca090de720ef0bdf04d..de0b9c071e0e8eea481446749f686fbc58525204 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -60,6 +60,8 @@ enum clk_ids {
        CLK_PLLETH_DIV_125_FIX,
        CLK_CSDIV_PLLETH_GBE0,
        CLK_CSDIV_PLLETH_GBE1,
+       CLK_SMUX2_DSI0_CLK,
+       CLK_SMUX2_DSI1_CLK,
        CLK_SMUX2_GBE0_TXCLK,
        CLK_SMUX2_GBE0_RXCLK,
        CLK_SMUX2_GBE1_TXCLK,
@@ -143,6 +145,8 @@ RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
 #define PLLDSI1                PLL_PACK_LIMITS(0x160, 1, 1, &rzg3e_cpg_pll_dsi1_limits)
 
 /* Mux clock tables */
+static const char * const smux2_dsi0_clk[] = { ".plldsi0_div7", ".plldsi0_csdiv" };
+static const char * const smux2_dsi1_clk[] = { ".plldsi1_div7", ".plldsi1_csdiv" };
 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
 static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
@@ -218,6 +222,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
                       CSDIV1_DIVCTL3, dtable_2_16_plldsi),
        DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
        DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
+       DEF_PLLDSI_SMUX(".smux2_dsi0_clk", CLK_SMUX2_DSI0_CLK,
+                       SSEL3_SELCTL0, smux2_dsi0_clk),
+       DEF_PLLDSI_SMUX(".smux2_dsi1_clk", CLK_SMUX2_DSI1_CLK,
+                       SSEL3_SELCTL1, smux2_dsi1_clk),
 
        /* Core Clocks */
        DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 33bc3c27291c8932e68f18d8f6dfcdafdc3bd9f9..dec0f7b621d6662202342acccfbe1a2c978f4a39 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -121,6 +121,7 @@ struct fixed_mod_conf {
 
 #define CPG_SSEL0              (0x300)
 #define CPG_SSEL1              (0x304)
+#define CPG_SSEL3              (0x30C)
 #define CPG_CDDIV0             (0x400)
 #define CPG_CDDIV1             (0x404)
 #define CPG_CDDIV2             (0x408)
@@ -156,6 +157,8 @@ struct fixed_mod_conf {
 #define SSEL1_SELCTL1  SMUX_PACK(CPG_SSEL1, 4, 1)
 #define SSEL1_SELCTL2  SMUX_PACK(CPG_SSEL1, 8, 1)
 #define SSEL1_SELCTL3  SMUX_PACK(CPG_SSEL1, 12, 1)
+#define SSEL3_SELCTL0  SMUX_PACK(CPG_SSEL3, 0, 1)
+#define SSEL3_SELCTL1  SMUX_PACK(CPG_SSEL3, 4, 1)
 
 #define BUS_MSTOP_IDX_MASK     GENMASK(31, 16)
 #define BUS_MSTOP_BITS_MASK    GENMASK(15, 0)