arm64: dts: renesas: r9a08g046: Add wdt device node

The RZ/G3L SOC has 3 watchdog timer channels:
  - channel0 (wdt0) for Cortex-A55-CPU Non-Secure,
  - channel1 (wdt1) for Cortex-A55 CPU Secure,
  - channel2 (wdt2) for Cortex-M33 CPU.

Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505125921.149682-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 0cedf5a38291f245985c0fb1c78fa8db4f524e70..02a3029c058e2fdc050ad6b8e18f6a9bbf2dada1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -577,6 +577,20 @@
                        interrupt-controller;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };
+
+               wdt0: watchdog@12800800 {
+                       compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt";
+                       reg = <0 0x12800800 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>,
+                                <&cpg CPG_MOD R9A08G046_WDT0_CLK>;
+                       clock-names = "pclk", "oscclk";
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "wdt", "perrout";
+                       resets = <&cpg R9A08G046_WDT0_PRESETN>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
        };
 
        stmmac_axi_setup: stmmac-axi-config {