wifi: rtw89: pci: disable PCI PHY error flag 8

As the PHY error flag 8 works improperly, disable it to prevent false
alarm causing SER.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260515014433.16168-7-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index d0d1e2b996980fb3f92b7c5664e55a6b481518c8..c3f2d0df5846d876b944be65cca9ffa3d998935f 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -58,7 +58,7 @@
 #define B_AX_DIV                       GENMASK(15, 14)
 #define RAC_SET_PPR_V1                 0x31
 #define RAC_ANA40                      0x40
-#define PHY_ERR_IMR_DIS                        (BIT(9) | BIT(0))
+#define PHY_ERR_IMR_DIS                        (BIT(9) | BIT(8) | BIT(0))
 #define RAC_ANA41                      0x41
 #define PHY_ERR_FLAG_EN                        BIT(6)
 
@@ -963,6 +963,8 @@
 #define R_BE_PCIE_HRPWM 0x30C0
 #define R_BE_PCIE_CRPWM 0x30C4
 
+#define R_BE_PCIE_HCI2FW_ISR 0x30CC
+
 #define R_BE_L1_2_CTRL_HCILDO 0x3110
 #define B_BE_PM_CLKREQ_EXT_RB BIT(11)
 #define B_BE_PCIE_DIS_RTK_PRST_N_L1_2 BIT(10)

diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c
index 473d491eb3f41e0d89da447b106425e0cb5d53b6..6390980b8ee060bc1b4c6a14ff69328c6093a6d4 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci_be.c
+++ b/drivers/net/wireless/realtek/rtw89/pci_be.c
@@ -347,6 +347,7 @@ static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
 
        rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
        rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
+       rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
 }
 
 static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
@@ -843,6 +844,8 @@ clear_phy_isr:
                        rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
                                                  RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
                }
+
+               rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
        }
 
        rtw89_pci_basic_cfg(rtwdev, true);