SF devlink port creation and registration used the ECPF's PCI function
as pfnum. Extend this to support satellite PF controllers by introducing
mlx5_esw_sf_controller_to_pfnum() that maps a controller number to the
corresponding PF number, and use it in SF port attribute setup and SF
creation validation.
Reorder the checks in mlx5_devlink_sf_port_new() so that
mlx5_sf_table_supported() runs before attribute validation, since the
new helper requires the eswitch to be initialized.
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260521110843.367329-8-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
struct netdev_phys_item_id ppid = {};
u16 pfnum;
- pfnum = PCI_FUNC(dev->pdev->devfn);
+ pfnum = mlx5_esw_sf_controller_to_pfnum(dev, controller);
mlx5_esw_get_port_parent_id(dev, &ppid);
memcpy(dl_port->attrs.switch_id.id, &ppid.id[0], ppid.id_len);
dl_port->attrs.switch_id.id_len = ppid.id_len;
return PCI_FUNC(dev->pdev->devfn);
}
+u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 controller)
+{
+ struct mlx5_eswitch *esw = dev->priv.eswitch;
+ struct mlx5_esw_functions *esw_funcs;
+ int i;
+
+ if (!controller)
+ return PCI_FUNC(dev->pdev->devfn);
+
+ esw_funcs = &esw->esw_funcs;
+ for (i = 0; i < esw_funcs->num_spfs; i++)
+ if (controller == esw_funcs->spfs[i].host_number + 1)
+ return esw_funcs->spfs[i].pf_num;
+
+ return mlx5_esw_get_hpf_pf_num(dev);
+}
+
bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev)
{
struct mlx5_eswitch *esw = dev->priv.eswitch;
u16 *host_number);
u16 mlx5_esw_get_hpf_host_number(struct mlx5_core_dev *dev);
u16 mlx5_esw_get_hpf_pf_num(struct mlx5_core_dev *dev);
+u16 mlx5_esw_sf_controller_to_pfnum(struct mlx5_core_dev *dev, u32 controller);
bool mlx5_esw_has_spf_sfs(struct mlx5_core_dev *dev);
int mlx5_esw_vport_vhca_id_map(struct mlx5_eswitch *esw,
mlx5_sf_new_check_attr(struct mlx5_core_dev *dev, const struct devlink_port_new_attrs *new_attr,
struct netlink_ext_ack *extack)
{
+ u32 controller;
+
if (new_attr->flavour != DEVLINK_PORT_FLAVOUR_PCI_SF) {
NL_SET_ERR_MSG_MOD(extack, "Driver supports only SF port addition");
return -EOPNOTSUPP;
NL_SET_ERR_MSG_MOD(extack, "External controller is unsupported");
return -EOPNOTSUPP;
}
- if (new_attr->pfnum != PCI_FUNC(dev->pdev->devfn)) {
+ controller = new_attr->controller_valid ? new_attr->controller : 0;
+ if (new_attr->pfnum !=
+ mlx5_esw_sf_controller_to_pfnum(dev, controller)) {
NL_SET_ERR_MSG_MOD(extack, "Invalid pfnum supplied");
return -EOPNOTSUPP;
}
struct mlx5_sf_table *table = dev->priv.sf_table;
int err;
- err = mlx5_sf_new_check_attr(dev, new_attr, extack);
- if (err)
- return err;
-
if (!mlx5_sf_table_supported(dev)) {
NL_SET_ERR_MSG_MOD(extack, "SF ports are not supported.");
return -EOPNOTSUPP;
return -EOPNOTSUPP;
}
+ err = mlx5_sf_new_check_attr(dev, new_attr, extack);
+ if (err)
+ return err;
+
return mlx5_sf_add(dev, table, new_attr, extack, dl_port);
}