ptl->fmt2 == ptl_fmt2)
return 0;
+ /* If enabling PTL, check disable bitmap */
+ if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) {
+ if (!bitmap_empty(ptl->disable_bitmap,
+ AMDGPU_PTL_DISABLE_MAX)) {
+ dev_dbg(adev->dev,
+ "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n",
+ test_bit(AMDGPU_PTL_DISABLE_SYSFS,
+ ptl->disable_bitmap),
+ test_bit(AMDGPU_PTL_DISABLE_PROFILER,
+ ptl->disable_bitmap),
+ atomic_read(&ptl->disable_ref));
+ return 0;
+ }
+ }
+
return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2);
}
uint32_t ptl_state, fmt1, fmt2;
int ret;
bool enable;
+ bool bit_changed = false;
mutex_lock(&ptl->mutex);
if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) {
fmt2 = ptl->fmt2;
ptl_state = enable ? 1 : 0;
+ if (enable)
+ bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS,
+ ptl->disable_bitmap);
+
ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2);
if (ret) {
dev_err(adev->dev, "Failed to set PTL err = %d\n", ret);
+ if (enable && bit_changed)
+ set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap);
mutex_unlock(&ptl->mutex);
return ret;
}
+ if (!enable)
+ set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap);
+
mutex_unlock(&ptl->mutex);
+
return count;
}
goto out;
}
}
+ set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap);
pdd->ptl_disable_req = true;
out:
goto out;
if (atomic_dec_return(&ptl->disable_ref) == 0) {
+ clear_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap);
ret = kfd_ptl_control(pdd, true);
if (ret) {
atomic_inc(&ptl->disable_ref);
+ set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap);
dev_warn(adev->dev, "Failed to enable PTL on release: %d\n", ret);
goto out;
}
AMDGPU_PTL_FMT_INVALID = 7,
};
+enum amdgpu_ptl_disable_source {
+ AMDGPU_PTL_DISABLE_SYSFS = 0,
+ AMDGPU_PTL_DISABLE_PROFILER,
+ AMDGPU_PTL_DISABLE_MAX,
+};
struct amdgpu_ptl {
enum amdgpu_ptl_fmt fmt1;
enum amdgpu_ptl_fmt fmt2;
/* PTL disable reference counting */
atomic_t disable_ref;
struct mutex mutex;
+ DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX);
};
int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code,