]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100
authorChanghuang Liang <changhuang.liang@starfivetech.com>
Thu, 16 Apr 2026 06:47:47 +0000 (23:47 -0700)
committerThomas Gleixner <tglx@kernel.org>
Thu, 30 Apr 2026 10:53:04 +0000 (12:53 +0200)
The StarFive JH8100 SoC was discontinued before production. The newly
taped-out JHB100 SoC uses the same interrupt controller IP.

Rename the binding file, compatible string, and MAINTAINERS entry from
"jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated
by users, but they exist in the hardware. Mark them as optional.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com
Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml [moved from Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml with 68% similarity]
MAINTAINERS

similarity index 68%
rename from Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
rename to Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
index ada5788602d65ebac93b97c9314bef21cb3b2f50..d8a0a3862ae2c0855d48fe383b269a5b2f5ec9c4 100644 (file)
@@ -1,13 +1,13 @@
 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
+$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: StarFive External Interrupt Controller
 
 description:
-  StarFive SoC JH8100 contain a external interrupt controller. It can be used
+  StarFive SoC JHB100 contain a external interrupt controller. It can be used
   to handle high-level input interrupt signals. It also send the output
   interrupt signal to RISC-V PLIC.
 
@@ -16,19 +16,11 @@ maintainers:
 
 properties:
   compatible:
-    const: starfive,jh8100-intc
+    const: starfive,jhb100-intc
 
   reg:
     maxItems: 1
 
-  clocks:
-    description: APB clock for the interrupt controller
-    maxItems: 1
-
-  resets:
-    description: APB reset for the interrupt controller
-    maxItems: 1
-
   interrupts:
     maxItems: 1
 
@@ -40,8 +32,6 @@ properties:
 required:
   - compatible
   - reg
-  - clocks
-  - resets
   - interrupts
   - interrupt-controller
   - "#interrupt-cells"
@@ -51,10 +41,8 @@ additionalProperties: false
 examples:
   - |
     interrupt-controller@12260000 {
-      compatible = "starfive,jh8100-intc";
+      compatible = "starfive,jhb100-intc";
       reg = <0x12260000 0x10000>;
-      clocks = <&syscrg_ne 76>;
-      resets = <&syscrg_ne 13>;
       interrupts = <45>;
       interrupt-controller;
       #interrupt-cells = <1>;
index 2fb1c75afd16388f590a77c04e08d2d6d002f5cc..30626d0b1044daff03ffc6152de8835250c35b5a 100644 (file)
@@ -25536,7 +25536,7 @@ F:      drivers/phy/starfive/phy-jh7110-usb.c
 STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER
 M:     Changhuang Liang <changhuang.liang@starfivetech.com>
 S:     Supported
-F:     Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml
+F:     Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
 F:     drivers/irqchip/irq-starfive-jh8100-intc.c
 
 STATIC BRANCH/CALL