clk: mediatek: mt8192: use MUX_CLR_SET

The mfg_pll_sel mux has neither a clock gate nor an update register,
and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF.

While upd_shift being -1 (as s8) prevents the update path from
executing at runtime, the bogus upd_ofs value is still stored in the
struct.

Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed
fields.

Fixes: 710573dee31b4 ("clk: mediatek: Add MT8192 basic clocks support")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 50b43807c60cfbae3c23cc5b730698d19df8dc40..12c8890d922fe76fbe25ec5bd38c19c479af2d32 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -579,8 +579,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
                             dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
        MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
                             mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
-       MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
-                       mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
+       MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents,
+                  0x050, 0x054, 0x058, 18, 1),
        MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
                             camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
        /* CLK_CFG_5 */