arm64: dts: renesas: r9a08g046: Add ICU node

Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430125342.439755-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index e52498b3a745edfd83b47559f37ff9a35ae0c5a0..232a0e299df7a09eed42c6f1e4f50e50600b312e 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -210,6 +210,96 @@
                        /* placeholder */
                };
 
+               icu: interrupt-controller@11050000 {
+                       compatible = "renesas,r9a08g046-irqc";
+                       #interrupt-cells = <2>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       reg = <0 0x11050000 0 0x10000>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "nmi",
+                                         "irq0", "irq1", "irq2", "irq3",
+                                         "irq4", "irq5", "irq6", "irq7",
+                                         "irq8", "irq9", "irq10", "irq11",
+                                         "irq12", "irq13", "irq14", "irq15",
+                                         "tint0", "tint1", "tint2", "tint3",
+                                         "tint4", "tint5", "tint6", "tint7",
+                                         "tint8", "tint9", "tint10", "tint11",
+                                         "tint12", "tint13", "tint14", "tint15",
+                                         "tint16", "tint17", "tint18", "tint19",
+                                         "tint20", "tint21", "tint22", "tint23",
+                                         "tint24", "tint25", "tint26", "tint27",
+                                         "tint28", "tint29", "tint30", "tint31",
+                                         "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0",
+                                         "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3",
+                                         "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7";
+                       clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>,
+                                <&cpg CPG_MOD R9A08G046_IA55_PCLK>;
+                       clock-names = "clk", "pclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_IA55_RESETN>;
+               };
+
                sdhi1: mmc@11c10000 {
                        reg = <0x0 0x11c10000 0 0x10000>;
                        /* placeholder */