drm/amdgpu: Fix gfx_hqd_mask in mes 12.1

Same as compute and sdma, gfx_hqd_mask has been initialized properly in
amdgpu_mes_init. set_hw_res should use those initialization accordingly.
Hardcoding it causes the mismatch between driver and MES.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
index cec80127812652db6d86bdf6a5f7e3538cbc7d93..456dbbcfce1e88bf860c0e20ee6ae6a25f6490da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
@@ -633,17 +633,6 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
                        offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 }
 
-static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
-{
-       /*
-        * GFX V12 has only one GFX pipe, but 8 queues in it.
-        * GFX pipe 0 queue 0 is being used by Kernel queue.
-        * Set GFX pipe 0 queue 1-7 for MES scheduling
-        * mask = 1111 1110b
-        */
-       pkt->gfx_hqd_mask[0] = 0xFE;
-}
-
 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
                                        int pipe, int xcc_id)
 {
@@ -667,7 +656,9 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
                        mes_set_hw_res_pkt.compute_hqd_mask[i] =
                                mes->compute_hqd_mask[i];
 
-               mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
+               for (i = 0; i < MAX_GFX_PIPES; i++)
+                       mes_set_hw_res_pkt.gfx_hqd_mask[i] =
+                               mes->gfx_hqd_mask[i];
 
                for (i = 0; i < MAX_SDMA_PIPES; i++)
                        mes_set_hw_res_pkt.sdma_hqd_mask[i] =