drm/panel: simple: Add Displaytech DT050BTFT-PTS panel

Add support for the Displaytech DT050BTFT-PTS 5.0" (800x480) color TFT
LCD panel, connected over DPI. Timings are taken from the datasheet
from 16 Nov 2023 is available from Seacomp:

https://www.seacomp.com/sites/default/files/datasheets/DT050BTFT-Displaytech-Spec.pdf

Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260422210806.80948-3-marex@nabladev.com

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 5ba71a3b44dee8768a4bcda1bea335f22fb465e9..2fbb9dff0a34df45db67f301d61090e8b685330e 100644 (file)
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1902,6 +1902,39 @@ static const struct panel_desc dataimage_scf0700c48ggu18 = {
        .connector_type = DRM_MODE_CONNECTOR_DPI,
 };
 
+static const struct display_timing displaytech_dt050btft_pts_timing = {
+       /* The TYP pixel clock are recalculated from tV * tH * 60 Hz */
+       .pixelclock = { 30000000, 33264000, 50000000 },
+       .hactive = { 800, 800, 800 },
+       .hfront_porch = { 16, 210, 354 },
+       /* Datasheet Figure 3 indicates, that tHPW is part of tHBP */
+       .hback_porch = { 41, 26, 6 },
+       .hsync_len = { 1, 20, 40 },
+       .vactive = { 480, 480, 480 },
+       .vfront_porch = { 7, 22, 147 },
+       /* Datasheet Figure 2 indicates, that tVPW is part of tVBP */
+       .vback_porch = { 22, 13, 3 },
+       .vsync_len = { 1, 10, 20 },
+       .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
+                DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
+                DISPLAY_FLAGS_SYNC_POSEDGE,
+};
+
+static const struct panel_desc displaytech_dt050btft_pts = {
+       .timings = &displaytech_dt050btft_pts_timing,
+       .num_timings = 1,
+       .bpc = 8,
+       .size = {
+               .width = 108,
+               .height = 65,
+       },
+       .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+       .bus_flags = DRM_BUS_FLAG_DE_HIGH |
+                    DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
+                    DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
+       .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
 static const struct display_timing dlc_dlc0700yzg_1_timing = {
        .pixelclock = { 45000000, 51200000, 57000000 },
        .hactive = { 1024, 1024, 1024 },
@@ -5681,6 +5714,9 @@ static const struct of_device_id platform_of_match[] = {
        }, {
                .compatible = "dataimage,scf0700c48ggu18",
                .data = &dataimage_scf0700c48ggu18,
+       }, {
+               .compatible = "displaytech,dt050btft-pts",
+               .data = &displaytech_dt050btft_pts,
        }, {
                .compatible = "dlc,dlc0700yzg-1",
                .data = &dlc_dlc0700yzg_1,