PCI: dwc: Record integrated eDMA register window

Some DesignWare PCIe controllers integrate an eDMA block whose registers
are located in a dedicated register window.

The EP-side aux-resource code exposes an interrupt-emulation doorbell
register (DOORBELL_MMIO) from that window. Its location is derived from
the start of the eDMA register window plus the doorbell offset already
provided by dw-edma, and the window size is used to validate the
computed register location.

Record the physical base and size of the integrated eDMA register window
in struct dw_pcie so the EP-side DesignWare aux-resource provider can
construct that doorbell resource.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260414141514.1341429-3-den@valinux.co.jp

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index c11cf61b8319e66ca5b50915ffd1cc9691d54974..22164e0068a9e867dfa582c03899ed5eb8957b78 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
                        pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
                        if (IS_ERR(pci->edma.reg_base))
                                return PTR_ERR(pci->edma.reg_base);
+                       pci->edma_reg_phys = res->start;
+                       pci->edma_reg_size = resource_size(res);
                } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
                        pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
+                       pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;
+                       pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;
                }
        }
 

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 3e69ef60165b0e58d8f69edcc2abf48485b69a82..f3314ceff8d77ae5919c3c0bc26c3e1b36920204 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -544,6 +544,8 @@ struct dw_pcie {
        int                     max_link_speed;
        u8                      n_fts[2];
        struct dw_edma_chip     edma;
+       phys_addr_t             edma_reg_phys;
+       resource_size_t         edma_reg_size;
        bool                    l1ss_support;   /* L1 PM Substates support */
        struct clk_bulk_data    app_clks[DW_PCIE_NUM_APP_CLKS];
        struct clk_bulk_data    core_clks[DW_PCIE_NUM_CORE_CLKS];