clk: renesas: r9a08g046: Add WDT clocks and reset

Add WDT clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260330132349.149391-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index d47aeaea2d6e5ea10186581c5cb825d73bfaf017..a311e17958d14cb22b4150f684532381b62916a5 100644 (file)
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -218,6 +218,10 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
                                        MSTOP(BUS_REG1, BIT(2))),
        DEF_MOD("dmac_pclk",            R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
                                        MSTOP(BUS_REG1, BIT(3))),
+       DEF_MOD("wdt0_pclk",            R9A08G046_WDT0_PCLK, R9A08G046_CLK_P0, 0x548, 0,
+                                       MSTOP(BUS_REG0, BIT(0))),
+       DEF_MOD("wdt0_clk",             R9A08G046_WDT0_CLK, R9A08G046_OSCCLK, 0x548, 1,
+                                       MSTOP(BUS_REG0, BIT(0))),
        DEF_MOD("eth0_clk_axi",         R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0,
                                        MSTOP(BUS_PERI_COM, BIT(2))),
        DEF_MOD("eth1_clk_axi",         R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1,
@@ -270,6 +274,7 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
        DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
        DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
        DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
+       DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
        DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
        DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),