drm/amd/display: Update tmz field for LSDMA

[Why & How]
TMZ field should be 4-bits wide instead of 1.
Also add missing src/dst_cache_policy fields to
tiled copy struct.

Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 48c6fe9d9e29ff4222daeba06dda12157971f8eb..9d4e7badb9f908cf526d09b2189f231bbac3d4e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -2255,6 +2255,8 @@ bool dmub_lsdma_send_tiled_to_tiled_copy_command(
        lsdma_data->u.tiled_copy_data.data_format      = params.data_format;
        lsdma_data->u.tiled_copy_data.max_com          = params.max_com;
        lsdma_data->u.tiled_copy_data.max_uncom        = params.max_uncom;
+       lsdma_data->u.tiled_copy_data.cache_policy_src = params.src_cache_policy;
+       lsdma_data->u.tiled_copy_data.cache_policy_dst = params.dst_cache_policy;
 
        result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 6579cf9cce3c5e9ef50641f33d0c442c13da9e7a..ebcaf49e5961e710cb9194f9a73cbb31e8e7ff6c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -240,11 +240,11 @@ struct lsdma_linear_sub_window_copy_params {
        uint32_t src_slice_pitch;
        uint32_t dst_slice_pitch;
 
-       uint32_t tmz              : 1;
+       uint32_t tmz              : 4;
        uint32_t element_size     : 3;
        uint32_t src_cache_policy : 3;
        uint32_t dst_cache_policy : 3;
-       uint32_t padding          : 22;
+       uint32_t padding          : 19;
 };
 
 bool dmub_lsdma_send_linear_sub_window_copy_command(
@@ -286,12 +286,13 @@ struct lsdma_send_tiled_to_tiled_copy_command_params {
        uint32_t swizzle_mode     : 5;
        uint32_t element_size     : 3;
        uint32_t dcc              : 1;
-       uint32_t tmz              : 1;
+       uint32_t tmz              : 4;
        uint32_t read_compress    : 2;
        uint32_t write_compress   : 2;
        uint32_t max_com          : 2;
        uint32_t max_uncom        : 1;
-       uint32_t padding          : 9;
+       uint32_t src_cache_policy : 3;
+       uint32_t dst_cache_policy : 3;
 };
 
 bool dmub_lsdma_send_tiled_to_tiled_copy_command(