select V4L2_MEM2MEM_DEV
select QCOM_MDT_LOADER if ARCH_QCOM
select QCOM_SCM
+ select QCOM_UBWC_CONFIG
select VIDEOBUF2_DMA_CONTIG
help
This is a V4L2 driver for Qualcomm iris video accelerator
DECODER = BIT(1),
};
+struct qcom_ubwc_cfg_data;
+
/**
* struct iris_core - holds core parameters valid for all instances
*
* @resets: table of iris reset clocks
* @controller_resets: table of controller reset clocks
* @iris_platform_data: a structure for platform data
+ * @ubwc_cfg: UBWC configuration for the platform
* @state: current state of core
* @iface_q_table_daddr: device address for interface queue table memory
* @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory
struct reset_control_bulk_data *resets;
struct reset_control_bulk_data *controller_resets;
const struct iris_platform_data *iris_platform_data;
+ const struct qcom_ubwc_cfg_data *ubwc_cfg;
enum iris_core_state state;
dma_addr_t iface_q_table_daddr;
dma_addr_t sfr_daddr;
#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include <linux/soc/qcom/ubwc.h>
#include "iris_core.h"
#include "iris_ctrls.h"
core->iris_platform_data = of_device_get_match_data(core->dev);
+ core->ubwc_cfg = qcom_ubwc_config_get_data();
+ if (IS_ERR(core->ubwc_cfg))
+ return PTR_ERR(core->ubwc_cfg);
+
ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr,
iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core);
if (ret)