]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
media: iris: retrieve UBWC platform configuration
authorDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Sun, 25 Jan 2026 11:30:05 +0000 (13:30 +0200)
committerBryan O'Donoghue <bod@kernel.org>
Sun, 10 May 2026 10:16:54 +0000 (11:16 +0100)
Specifying UBWC data in each driver doesn't scale and is prone to
errors. Request UBWC data from the central database in preparation to
using it through the rest of the driver.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
drivers/media/platform/qcom/iris/Kconfig
drivers/media/platform/qcom/iris/iris_core.h
drivers/media/platform/qcom/iris/iris_probe.c

index 3c803a05305a80b404cd3659b906987f065f22ac..39b06de6c3e6e2dbd96c2ef62c791d796580e708 100644 (file)
@@ -5,6 +5,7 @@ config VIDEO_QCOM_IRIS
         select V4L2_MEM2MEM_DEV
         select QCOM_MDT_LOADER if ARCH_QCOM
         select QCOM_SCM
+        select QCOM_UBWC_CONFIG
         select VIDEOBUF2_DMA_CONTIG
         help
           This is a V4L2 driver for Qualcomm iris video accelerator
index fb194c967ad4f9b5e00cd74f0d41e0b827ef14db..d10a03aa5685ac1711bb4d504a8928bd5d62d2e0 100644 (file)
@@ -30,6 +30,8 @@ enum domain_type {
        DECODER = BIT(1),
 };
 
+struct qcom_ubwc_cfg_data;
+
 /**
  * struct iris_core - holds core parameters valid for all instances
  *
@@ -52,6 +54,7 @@ enum domain_type {
  * @resets: table of iris reset clocks
  * @controller_resets: table of controller reset clocks
  * @iris_platform_data: a structure for platform data
+ * @ubwc_cfg: UBWC configuration for the platform
  * @state: current state of core
  * @iface_q_table_daddr: device address for interface queue table memory
  * @sfr_daddr: device address for SFR (Sub System Failure Reason) register memory
@@ -95,6 +98,7 @@ struct iris_core {
        struct reset_control_bulk_data          *resets;
        struct reset_control_bulk_data          *controller_resets;
        const struct iris_platform_data         *iris_platform_data;
+       const struct qcom_ubwc_cfg_data         *ubwc_cfg;
        enum iris_core_state                    state;
        dma_addr_t                              iface_q_table_daddr;
        dma_addr_t                              sfr_daddr;
index ddaacda523ecb9990af0dd0640196223fbcc2cab..492f85f518ebaba7648e368b0680535740e3d541 100644 (file)
@@ -10,6 +10,7 @@
 #include <linux/pm_opp.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
+#include <linux/soc/qcom/ubwc.h>
 
 #include "iris_core.h"
 #include "iris_ctrls.h"
@@ -244,6 +245,10 @@ static int iris_probe(struct platform_device *pdev)
 
        core->iris_platform_data = of_device_get_match_data(core->dev);
 
+       core->ubwc_cfg = qcom_ubwc_config_get_data();
+       if (IS_ERR(core->ubwc_cfg))
+               return PTR_ERR(core->ubwc_cfg);
+
        ret = devm_request_threaded_irq(core->dev, core->irq, iris_hfi_isr,
                                        iris_hfi_isr_handler, IRQF_TRIGGER_HIGH, "iris", core);
        if (ret)