arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay

The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the
MAC driver to additionally insert internal TX/RX delays, resulting in
double delay being applied and causing Ethernet link timing issues.

Change phy-mode to "rgmii" across all Agilex5 device tree files to
reflect that the clock delay is already handled by the hardware and
no additional software-inserted delay is required. Add an inline comment
to satisfy checkpatch and document the hardware-provided delay.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index dae0db9f881943d4e580cdf1aaf1e7db49a4b4d1..57d3c5807c65c7de1838ff5d601a2689efd10830 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -44,7 +44,7 @@
 
 &gmac2 {
        status = "okay";
-       phy-mode = "rgmii-id";
+       phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
        phy-handle = <&emac2_phy0>;
        max-frame-size = <9000>;
 

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index 86137380df0449593304d83bcc5858e492f6243f..82cd4115746ec44c80e45610884acb5a2af21d52 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -43,7 +43,7 @@
 
 &gmac2 {
        status = "okay";
-       phy-mode = "rgmii-id";
+       phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
        phy-handle = <&emac2_phy0>;
        max-frame-size = <9000>;
 

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index e728cedb4cbd53046eb997e76f81f15d0c3b5a57..4d32b6928ce1791e4c405fccaba908ad375580f5 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -46,7 +46,7 @@
 
 &gmac2 {
        status = "okay";
-       phy-mode = "rgmii-id";
+       phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
        phy-handle = <&emac2_phy0>;
        max-frame-size = <9000>;
 

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index 21faa47681fad938c191a63f1b337ac195a0e5ec..81443096cf991dafa6027d471d65372471364007 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -41,7 +41,7 @@
 
 &gmac0 {
        status = "okay";
-       phy-mode = "rgmii-id";
+       phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
        phy-handle = <&emac0_phy0>;
        max-frame-size = <9000>;